📄 regs240x.h
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#define CANRCR *((volatile int *)0x7102) /* CAN Recieve COntrol Reg */
#define CANMCR *((volatile int *)0x7103) /* CAN Master Control Reg */
#define CANBCR2 *((volatile int *)0x7104) /* CAN Bit COnfig Reg 2 */
#define CANBCR1 *((volatile int *)0x7105) /* CAN Bit Config Reg 1 */
#define CANESR *((volatile int *)0x7106) /* CAN Error Status Reg */
#define CANGSR *((volatile int *)0x7107) /* CAN Global Status Reg */
#define CANCEC *((volatile int *)0x7108) /* CAN Trans and Rcv Err counters */
#define CANIFR *((volatile int *)0x7109) /* CAN Interrupt Flag Registers */
#define CANIMR *((volatile int *)0x710a) /* CAN Interrupt Mask Registers */
#define CANLAM0H *((volatile int *)0x710b) /* CAN Local Acceptance Mask MBx0/1 */
#define CANLAM0L *((volatile int *)0x710c) /* CAN Local Acceptance Mask MBx0/1 */
#define CANLAM1H *((volatile int *)0x710d) /* CAN Local Acceptance Mask MBx2/3 */
#define CANLAM1L *((volatile int *)0x710e) /* CAN Local Acceptance Mask MBx2/3 */
#define CANMSGID0L *((volatile int *)0x7200) /* CAN Message ID for mailbox 0 (lower */
#define CANMSGID0H *((volatile int *)0x7201) /* CAN Message ID for mailbox 0 (upper */
#define CANMSGCTRL0 *((volatile int *)0x7202) /* CAN RTR and DLC */
#define CANMBX0A *((volatile int *)0x7204) /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMBX0B *((volatile int *)0x7205) /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMBX0C *((volatile int *)0x7206) /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMBX0D *((volatile int *)0x7207) /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMSGID1L *((volatile int *)0x7208) /* CAN Message ID for mailbox 1 (lower */
#define CANMSGID1H *((volatile int *)0x7209) /* CAN Message ID for mailbox 1 (upper */
#define CANMSGCTRL1 *((volatile int *)0x720A) /* CAN RTR and DLC */
#define CANMBX1A *((volatile int *)0x720C) /* CAN 2 of 8 bytes of Mailbox 1 */
#define CANMBX1B *((volatile int *)0x720D) /* CAN 2 of 8 bytes of Mailbox 1 */
#define CANMBX1C *((volatile int *)0x720E) /* CAN 2 of 8 bytes of Mailbox 1 */
#define CANMBX1D *((volatile int *)0x720F) /* CAN 2 of 8 bytes of Mailbox 1 */
#define CANMSGID2L *((volatile int *)0x7210) /* CAN Message ID for mailbox 2 (lower */
#define CANMSGID2H *((volatile int *)0x7211) /* CAN Message ID for mailbox 2 (upper */
#define CANMSGCTRL2 *((volatile int *)0x7212) /* CAN RTR and DLC */
#define CANMBX2A *((volatile int *)0x7214) /* CAN 2 of 8 bytes of Mailbox 2 */
#define CANMBX2B *((volatile int *)0x7215) /* CAN 2 of 8 bytes of Mailbox 2 */
#define CANMBX2C *((volatile int *)0x7216) /* CAN 2 of 8 bytes of Mailbox 2 */
#define CANMBX2D *((volatile int *)0x7217) /* CAN 2 of 8 bytes of Mailbox 2 */
#define CANMSGID3L *((volatile int *)0x7218) /* CAN Message ID for mailbox 3 (lower */
#define CANMSGID3H *((volatile int *)0x7219) /* CAN Message ID for mailbox 3 (upper */
#define CANMSGCTRL3 *((volatile int *)0x721A) /* CAN RTR and DLC */
#define CANMBX3A *((volatile int *)0x721C) /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMBX3B *((volatile int *)0x721D) /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMBX3C *((volatile int *)0x721E) /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMBX3D *((volatile int *)0x721F) /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMSGID4L *((volatile int *)0x7220) /* CAN Message ID for mailbox 4 (lower */
#define CANMSGID4H *((volatile int *)0x7221) /* CAN Message ID for mailbox 4 (upper */
#define CANMSGCTRL4 *((volatile int *)0x7222) /* CAN RTR and DLC */
#define CANMBX4A *((volatile int *)0x7224) /* CAN 2 of 8 bytes of Mailbox 4 */
#define CANMBX4B *((volatile int *)0x7225) /* CAN 2 of 8 bytes of Mailbox 4 */
#define CANMBX4C *((volatile int *)0x7226) /* CAN 2 of 8 bytes of Mailbox 4 */
#define CANMBX4D *((volatile int *)0x7227) /* CAN 2 of 8 bytes of Mailbox 4 */
#define CANMSGID5L *((volatile int *)0x7228) /* CAN Message ID for mailbox 5 (lower */
#define CANMSGID5H *((volatile int *)0x7229) /* CAN Message ID for mailbox 5 (upper */
#define CANMSGCTRL5 *((volatile int *)0x722A) /* CAN RTR and DLC */
#define CANMBX5A *((volatile int *)0x722C) /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5B *((volatile int *)0x722D) /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5C *((volatile int *)0x722E) /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5D *((volatile int *)0x722F) /* CAN 2 of 8 bytes of Mailbox 5 */
/*--------------------------------------------------------------------------*/
/* I/O space mapped registers */
/*--------------------------------------------------------------------------*/
#define WSGR portffff
ioport unsigned portffff; /* Wait-State Generator Control Reg */
#define FCMR portff0f /* Flash mode control register */
ioport unsigned portff0f;
ioport unsigned port0;
ioport unsigned port1;
ioport unsigned port2;
ioport unsigned port3;
ioport unsigned port4;
#define DAC0 port0
#define DAC1 port1
#define DAC2 port2
#define DAC3 port3
#define DACL port4
#endif /*__REGS240X_H__ */
/*
//=====================================================================
// Filename: f2407_c.h
// Author: David M. Alter, Texas Instruments Inc.
// Description: LF2407 DSP register definitions for C-code.
// History: 03/14/01 - original (D. Alter)
// 08/12/02 - fixed addresses of CAP2FBOT, CAP3FBOT,
// CAP5FBOT, and CAP6FBOT. (D. Alter)
//=====================================================================
Core registers
#define IMR (volatile unsigned int *)0x0004 // Interrupt mask reg
#define GREG (volatile unsigned int *)0x0005 // Global memory allocation reg
#define IFR (volatile unsigned int *)0x0006 // Interrupt flag reg
System configuration and interrupt registers
#define PIRQR0 (volatile unsigned int *)0x7010 // Peripheral interrupt request reg 0
#define PIRQR1 (volatile unsigned int *)0x7011 // Peripheral interrupt request reg 1
#define PIRQR2 (volatile unsigned int *)0x7012 // Peripheral interrupt request reg 2
#define PIACKR0 (volatile unsigned int *)0x7014 // Peripheral interrupt acknowledge reg 0
#define PIACKR1 (volatile unsigned int *)0x7015 // Peripheral interrupt acknowledge reg 1
#define PIACKR2 (volatile unsigned int *)0x7016 // Peripheral interrupt acknowledge reg 2
#define SCSR1 (volatile unsigned int *)0x7018 // System control & status reg 1
#define SCSR2 (volatile unsigned int *)0x7019 // System control & status reg 2
#define DINR (volatile unsigned int *)0x701C // Device identification reg
#define PIVR (volatile unsigned int *)0x701E // Peripheral interrupt vector reg
Watchdog timer (WD) registers
#define WDCNTR (volatile unsigned int *)0x7023 // WD counter reg
#define WDKEY (volatile unsigned int *)0x7025 // WD reset key reg
#define WDCR (volatile unsigned int *)0x7029 // WD timer control reg
Serial Peripheral Interface (SPI) registers
#define SPICCR (volatile unsigned int *)0x7040 // SPI configuration control reg
#define SPICTL (volatile unsigned int *)0x7041 // SPI operation control reg
#define SPISTS (volatile unsigned int *)0x7042 // SPI status reg
#define SPIBRR (volatile unsigned int *)0x7044 // SPI baud rate reg
#define SPIRXEMU (volatile unsigned int *)0x7046 // SPI emulation buffer reg
#define SPIRXBUF (volatile unsigned int *)0x7047 // SPI serial receive buffer reg
#define SPITXBUF (volatile unsigned int *)0x7048 // SPI serial transmit buffer reg
#define SPIDAT (volatile unsigned int *)0x7049 // SPI serial data reg
#define SPIPRI (volatile unsigned int *)0x704F // SPI priority control reg
SCI registers
#define SCICCR (volatile unsigned int *)0x7050 // SCI communication control reg
#define SCICTL1 (volatile unsigned int *)0x7051 // SCI control reg 1
#define SCIHBAUD (volatile unsigned int *)0x7052 // SCI baud-select reg, high bits
#define SCILBAUD (volatile unsigned int *)0x7053 // SCI baud-select reg, low bits
#define SCICTL2 (volatile unsigned int *)0x7054 // SCI control reg 2
#define SCIRXST (volatile unsigned int *)0x7055 // SCI receiver status reg
#define SCIRXEMU (volatile unsigned int *)0x7056 // SCI emulation data buffer reg
#define SCIRXBUF (volatile unsigned int *)0x7057 // SCI receiver data buffer reg
#define SCITXBUF (volatile unsigned int *)0x7059 // SCI transmit data buffer reg
#define SCIPRI (volatile unsigned int *)0x705F // SCI priority control reg
External interrupt configuration registers
#define XINT1CR (volatile unsigned int *)0x7070 // Ext interrupt 1 config reg
#define XINT2CR (volatile unsigned int *)0x7071 // Ext interrupt 2 config reg
Digital I/O registers
#define MCRA (volatile unsigned int *)0x7090 // I/O mux control reg A
#define MCRB (volatile unsigned int *)0x7092 // I/O mux control reg B
#define MCRC (volatile unsigned int *)0x7094 // I/O mux control reg C
#define PADATDIR (volatile unsigned int *)0x7098 // I/O port A data & dir reg
#define PBDATDIR (volatile unsigned int *)0x709A // I/O port B data & dir reg
#define PCDATDIR (volatile unsigned int *)0x709C // I/O port C data & dir reg
#define PDDATDIR (volatile unsigned int *)0x709E // I/O port D data & dir reg
#define PEDATDIR (volatile unsigned int *)0x7095 // I/O port E data & dir reg
#define PFDATDIR (volatile unsigned int *)0x7096 // I/O port F data & dir reg
Analog-to-Digital Converter (ADC) registers
#define ADCTRL1 (volatile unsigned int *)0x70A0 // ADC control reg 1
#define ADCTRL2 (volatile unsigned int *)0x70A1 // ADC control reg 2
#define MAX_CONV (volatile unsigned int *)0x70A2 // Maximum conversion channels reg
#define CHSELSEQ1 (volatile unsigned int *)0x70A3 // Channel select sequencing control reg 1
#define CHSELSEQ2 (volatile unsigned int *)0x70A4 // Channel select sequencing control reg 2
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