example_2833xda.gel

TMS32028335 的一些例程

    GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");

    GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
    GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
    GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
    GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
    GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
    GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
    GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
    GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
    GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");

    GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
    GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
    GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
    GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
    GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
    GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
    GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
    GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
    GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");


}
hotmenu DMA_Channel_1_regs()
{
    GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
    GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
    GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
    GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
    GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
    GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");
}

hotmenu DMA_Channel_2_regs()
{
    GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
    GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
    GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
    GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
    GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
    GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_3_regs()
{
    GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
    GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
    GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
    GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
    GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
    GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_4_regs()
{
    GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
    GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
    GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
    GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
    GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
    GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x108A,x","DMA Ch4 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x108B,x","DMA Ch4 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x108C,x","DMA Ch4 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x108D,x","DMA Ch4 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x108E,x","DMA Ch4 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x108F,x","DMA Ch4 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1090,x","DMA Ch4 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1092,x","DMA Ch4 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1094,x","DMA Ch4 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1096,x","DMA Ch4 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1098,x","DMA Ch4 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x109A,x","DMA Ch4 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x109C,x","DMA Ch4 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x109E,x","DMA Ch4 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_5_regs()
{
    GEL_WatchAdd("*0x10A0,x","DMA Ch5 MODE");
    GEL_WatchAdd("*0x10A1,x","DMA Ch5 CONTROL");
    GEL_WatchAdd("*0x10A2,x","DMA Ch5 BURST_SIZE");
    GEL_WatchAdd("*0x10A3,x","DMA Ch5 BURST_COUNT");
    GEL_WatchAdd("*0x10A4,x","DMA Ch5 SRC_BURST_STEP");
    GEL_WatchAdd("*0x10A5,x","DMA Ch5 DST_BURST_STEP");
    GEL_WatchAdd("*0x10A6,x","DMA Ch5 TRANSFER_SIZE");
    GEL_WatchAdd("*0x10A7,x","DMA Ch5 TRANSFER_COUNT");
    GEL_WatchAdd("*0x10A8,x","DMA Ch5 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x10A9,x","DMA Ch5 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x10AA,x","DMA Ch5 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x10AB,x","DMA Ch5 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x10AC,x","DMA Ch5 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x10AD,x","DMA Ch5 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x10AE,x","DMA Ch5 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x10AF,x","DMA Ch5 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x10B0,x","DMA Ch5 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10B2,x","DMA Ch5 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10B4,x","DMA Ch5 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10B6,x","DMA Ch5 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10B8,x","DMA Ch5 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10BA,x","DMA Ch5 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10BC,x","DMA Ch5 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10BE,x","DMA Ch5 DST_ADDR_ACTIVE");
}
hotmenu DMA_Channel_6_regs()
{
    GEL_WatchAdd("*0x10C0,x","DMA Ch6 MODE");
    GEL_WatchAdd("*0x10C1,x","DMA Ch6 CONTROL");
    GEL_WatchAdd("*0x10C2,x","DMA Ch6 BURST_SIZE");
    GEL_WatchAdd("*0x10C3,x","DMA Ch6 BURST_COUNT");
    GEL_WatchAdd("*0x10C4,x","DMA Ch6 SRC_BURST_STEP");
    GEL_WatchAdd("*0x10C5,x","DMA Ch6 DST_BURST_STEP");
    GEL_WatchAdd("*0x10C6,x","DMA Ch6 TRANSFER_SIZE");
    GEL_WatchAdd("*0x10C7,x","DMA Ch6 TRANSFER_COUNT");
    GEL_WatchAdd("*0x10C8,x","DMA Ch6 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x10C9,x","DMA Ch6 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x10CA,x","DMA Ch6 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x10CB,x","DMA Ch6 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x10CC,x","DMA Ch6 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x10CD,x","DMA Ch6 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x10CE,x","DMA Ch6 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x10CF,x","DMA Ch6 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x10D0,x","DMA Ch6 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10D2,x","DMA Ch6 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10D4,x","DMA Ch6 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10D6,x","DMA Ch6 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10D8,x","DMA Ch6 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10DA,x","DMA Ch6 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x10DC,x","DMA Ch6 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x10DE,x","DMA Ch6 DST_ADDR_ACTIVE");
}

/********************************************************************/
/* eCAN Registers                                                   */
/********************************************************************/
menuitem "Watch eCAN Registers";

hotmenu eCAN_A_Global_Regs()
{
    GEL_WatchAdd("*(long *)0x6000,x","eCANA CANME");
    GEL_WatchAdd("*(long *)0x6002,x","eCANA CANMD");
    GEL_WatchAdd("*(long *)0x6004,x","eCANA CANTRS");
    GEL_WatchAdd("*(long *)0x6006,x","eCANA CANTRR");
    GEL_WatchAdd("*(long *)0x6008,x","eCANA CANTA");
    GEL_WatchAdd("*(long *)0x600A,x","eCANA CANAA");
    GEL_WatchAdd("*(long *)0x600C,x","eCANA CANRMP");
    GEL_WatchAdd("*(long *)0x600E,x","eCANA CANRML");
    GEL_WatchAdd("*(long *)0x6010,x","eCANA CANRFP");
    GEL_WatchAdd("*(long *)0x6014,x","eCANA CANMC");
    GEL_WatchAdd("*(long *)0x6016,x","eCANA CANBTC");
    GEL_WatchAdd("*(long *)0x6018,x","eCANA CANES");
    GEL_WatchAdd("*(long *)0x601A,x","eCANA CANTEC");
    GEL_WatchAdd("*(long *)0x601C,x","eCANA CANREC");
    GEL_WatchAdd("*(long *)0x601E,x","eCANA CANGIF0");
    GEL_WatchAdd("*(long *)0x6020,x","eCANA CANGIM");
    GEL_WatchAdd("*(long *)0x6022,x","eCANA CANGIF1");
    GEL_WatchAdd("*(long *)0x6024,x","eCANA CANMIM");
    GEL_WatchAdd("*(long *)0x6026,x","eCANA CANMIL");
    GEL_WatchAdd("*(long *)0x6028,x","eCANA CANOPC");
    GEL_WatchAdd("*(long *)0x602A,x","eCANA CANTIOC");
    GEL_WatchAdd("*(long *)0x602C,x","eCANA CANRIOC");
    GEL_WatchAdd("*(long *)0x602E,x","eCANA CANLNT");
    GEL_WatchAdd("*(long *)0x6030,x","eCANA CANTOC");
    GEL_WatchAdd("*(long *)0x6032,x","eCANA CANTOS");
}
hotmenu eCAN_A_Mailbox_0_to_1_Regs()
{
    GEL_WatchAdd("*(long *)0x6040,x","eCANA LAM0");
    GEL_WatchAdd("*(long *)0x6080,x","eCANA MOTS0");
    GEL_WatchAdd("*(long *)0x60C0,x","eCANA MOTO0");
    GEL_WatchAdd("*(long *)0x6100,x","eCANA MID0");
    GEL_WatchAdd("*(long *)0x6102,x","eCANA MCF0");
    GEL_WatchAdd("*(long *)0x6104,x","eCANA MDL0");
    GEL_WatchAdd("*(long *)0x6106,x","eCANA MDH0");
    
    GEL_WatchAdd("*(long *)0x6042,x","eCANA LAM1");
    GEL_WatchAdd("*(long *)0x6082,x","eCANA MOTS1");
    GEL_WatchAdd("*(long *)0x60C2,x","eCANA MOTO1");
    GEL_WatchAdd("*(long *)0x6108,x","eCANA MID1");
    GEL_WatchAdd("*(long *)0x610A,x","eCANA MCF1");
    GEL_WatchAdd("*(long *)0x610C,x","eCANA MDL1");
    GEL_WatchAdd("*(long *)0x610E,x","eCANA MDH1");
}
hotmenu eCAN_A_Mailbox_2_to_3_Regs()
{
    GEL_WatchAdd("*(long *)0x6044,x","eCANA LAM2");
    GEL_WatchAdd("*(long *)0x6084,x","eCANA MOTS2");
    GEL_WatchAdd("*(long *)0x60C4,x","eCANA MOTO2");
    GEL_WatchAdd("*(long *)0x6110,x","eCANA MID2");
    GEL_WatchAdd("*(long *)0x6112,x","eCANA MCF2");
    GEL_WatchAdd("*(long *)0x6114,x","eCANA MDL2");
    GEL_WatchAdd("*(long *)0x6116,x","eCANA MDH2");

    GEL_WatchAdd("*(long *)0x6046,x","eCANA LAM3");
    GEL_WatchAdd("*(long *)0x6086,x","eCANA MOTS3");
    GEL_WatchAdd("*(long *)0x60C6,x","eCANA MOTO3");
    GEL_WatchAdd("*(long *)0x6118,x","eCANA MID3");
    GEL_WatchAdd("*(long *)0x611A,x","eCANA MCF3");
    GEL_WatchAdd("*(long *)0x611C,x","eCANA MDL3");
    GEL_WatchAdd("*(long *)0x611E,x","eCANA MDH3");
}
hotmenu eCAN_A_Mailbox_4_to_5_Regs()
{
    GEL_WatchAdd("*(long *)0x6048,x","eCANA LAM4");
    GEL_WatchAdd("*(long *)0x6088,x","eCANA MOTS4");
    GEL_WatchAdd("*(long *)0x60C8,x","eCANA MOTO4");
    GEL_WatchAdd("*(long *)0x6120,x","eCANA MID4");
    GEL_WatchAdd("*(long *)0x6122,x","eCANA MCF4");
    GEL_WatchAdd("*(long *)0x6124,x","eCANA MDL4");
    GEL_WatchAdd("*(long *)0x6126,x","eCANA MDH4");