example_2833xda.gel

TMS32028335 的一些例程

    GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");

    GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
    GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
    GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
    GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
    GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
    GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
    GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
    GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
    GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
    GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
    GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
    GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
    GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
    GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
    GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
    GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}
hotmenu ADC_Control_Regs()
{
    GEL_WatchAdd("*0x7100,x","ADCTRL1");
    GEL_WatchAdd("*0x7101,x","ADCTRL2");
    GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
    GEL_WatchAdd("*0x7107,x","ADCASEQSR");
    GEL_WatchAdd("*0x7118,x","ADCTRL3");
    GEL_WatchAdd("*0x7119,x","ADCST");
    GEL_WatchAdd("*0x711C,x","ADCREFSEL");
    GEL_WatchAdd("*0x711D,x","ADCOFFTRIM");
}
hotmenu ADCCHSELSEQx_Regs()
{
    GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
    GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
    GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
    GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCRESULT_0_to_7()
{
    GEL_WatchAdd("*0x7108,x","ADCRESULT0");
    GEL_WatchAdd("*0x7109,x","ADCRESULT1");
    GEL_WatchAdd("*0x710A,x","ADCRESULT2");
    GEL_WatchAdd("*0x710B,x","ADCRESULT3");
    GEL_WatchAdd("*0x710C,x","ADCRESULT4");
    GEL_WatchAdd("*0x710D,x","ADCRESULT5");
    GEL_WatchAdd("*0x710E,x","ADCRESULT6");
    GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_15()
{
    GEL_WatchAdd("*0x7110,x","ADCRESULT8");
    GEL_WatchAdd("*0x7111,x","ADCRESULT9");
    GEL_WatchAdd("*0x7112,x","ADCRESULT10");
    GEL_WatchAdd("*0x7113,x","ADCRESULT11");
    GEL_WatchAdd("*0x7114,x","ADCRESULT12");
    GEL_WatchAdd("*0x7115,x","ADCRESULT13");
    GEL_WatchAdd("*0x7116,x","ADCRESULT14");
    GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCRESULT_Mirror_0_to_7()
{
    GEL_WatchAdd("*0x0B00,x","ADCRESULT0 Mirror");
    GEL_WatchAdd("*0x0B01,x","ADCRESULT1 Mirror");
    GEL_WatchAdd("*0x0B02,x","ADCRESULT2 Mirror");
    GEL_WatchAdd("*0x0B03,x","ADCRESULT3 Mirror");
    GEL_WatchAdd("*0x0B04,x","ADCRESULT4 Mirror");
    GEL_WatchAdd("*0x0B05,x","ADCRESULT5 Mirror");
    GEL_WatchAdd("*0x0B06,x","ADCRESULT6 Mirror");
    GEL_WatchAdd("*0x0B07,x","ADCRESULT7 Mirror");
}
hotmenu ADCRESULT_Mirror_8_to_15()
{
    GEL_WatchAdd("*0x0B08,x","ADCRESULT8 Mirror");
    GEL_WatchAdd("*0x0B09,x","ADCRESULT9 Mirror");
    GEL_WatchAdd("*0x0B0A,x","ADCRESULT10 Mirror");
    GEL_WatchAdd("*0x0B0B,x","ADCRESULT11 Mirror");
    GEL_WatchAdd("*0x0B0C,x","ADCRESULT12 Mirror");
    GEL_WatchAdd("*0x0B0D,x","ADCRESULT13 Mirror");
    GEL_WatchAdd("*0x0B0E,x","ADCRESULT14 Mirror");
    GEL_WatchAdd("*0x0B0F,x","ADCRESULT15 Mirror");
}


/********************************************************************/
/* Clocking and Low-Power Registers                                 */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";

hotmenu All_Clocking_and_Low_Power_Regs()
{
    GEL_WatchAdd("*0x7010,x","XCLK");
    GEL_WatchAdd("*0x7011,x","PLLSTS");
    GEL_WatchAdd("*0x701A,x","HISPCP");
    GEL_WatchAdd("*0x701B,x","LOSPCP");
    GEL_WatchAdd("*0x701C,x","PCLKCR0");
    GEL_WatchAdd("*0x701D,x","PCLKCR1");
    GEL_WatchAdd("*0x701E,x","LPMCR0");
    GEL_WatchAdd("*0x7020,x","PCLKCR3");
    GEL_WatchAdd("*0x7021,x","PLLCR");
}
hotmenu XCLK()
{
    GEL_WatchAdd("*0x7010,x","XCLK");
}
hotmenu PLLSTS()
{
    GEL_WatchAdd("*0x7011,x","PLLSTS");
}
hotmenu HISPCP()
{
    GEL_WatchAdd("*0x701A,x","HISPCP");
}
hotmenu LOSPCP()
{
    GEL_WatchAdd("*0x701B,x","LOSPCP");
}
hotmenu PCLKCR0()
{
    GEL_WatchAdd("*0x701C,x","PCLKCR0");
}
hotmenu PCLKCR1()
{
    GEL_WatchAdd("*0x701D,x","PCLKCR1");
}
hotmenu PCLKCR3()
{
    GEL_WatchAdd("*0x7020,x","PCLKCR3");
}
hotmenu LPMCR0()
{
    GEL_WatchAdd("*0x701E,x","LPMCR0");
}
hotmenu PLLCR()
{
    GEL_WatchAdd("*0x7021,x","PLLCR");
}


/********************************************************************/
/* Code Security Module Registers                                   */
/********************************************************************/
menuitem "Watch Code Security Module Registers";

hotmenu CSMSCR()
{
    GEL_WatchAdd("*0x0AEF,x","CSMSCR");
    GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
    GEL_WatchAdd("(*0x0AEF)&1,d","     SECURE bit");
}
hotmenu PWL_Locations()
{
    GEL_WatchAdd("*0x33FFF8,x","PWL0");
    GEL_WatchAdd("*0x33FFF9,x","PWL1");
    GEL_WatchAdd("*0x33FFFA,x","PWL2");
    GEL_WatchAdd("*0x33FFFB,x","PWL3");
    GEL_WatchAdd("*0x33FFFC,x","PWL4");
    GEL_WatchAdd("*0x33FFFD,x","PWL5");
    GEL_WatchAdd("*0x33FFFE,x","PWL6");
    GEL_WatchAdd("*0x33FFFF,x","PWL7");
}


/********************************************************************/
/* CPU Timer Registers                                              */
/********************************************************************/
menuitem "Watch CPU Timer Registers";

hotmenu All_CPU_Timer0_Regs()
{
    GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
    GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
    GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
    GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
    GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
    GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
    GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
    GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
    GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
    GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
    GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
    GEL_WatchAdd("*0x0C0C,x","TIMER1TCR");
    GEL_WatchAdd("*0x0C0E,x","TIMER1TPR");
    GEL_WatchAdd("*0x0C0F,x","TIMER1TPRH");
}
hotmenu All_CPU_Timer2_Regs()
{
    GEL_WatchAdd("*0x0C10,x","TIMER2TIM");
    GEL_WatchAdd("*0x0C11,x","TIMER2TIMH");
    GEL_WatchAdd("*0x0C12,x","TIMER2PRD");
    GEL_WatchAdd("*0x0C13,x","TIMER2PRDH");
    GEL_WatchAdd("*0x0C14,x","TIMER2TCR");
    GEL_WatchAdd("*0x0C16,x","TIMER2TPR");
    GEL_WatchAdd("*0x0C17,x","TIMER2TPRH");
}


/********************************************************************/
/* Device Emulation Registers                                       */
/********************************************************************/
menuitem "Watch Device Emulation Registers";

hotmenu All_Emulation_Regs()
{
    GEL_WatchAdd("*(long *)0x0880,x","DEVICECNF");
    GEL_WatchAdd("*0x0882,x","PARTID");
    GEL_WatchAdd("*0x0883,x","REVID");
    GEL_WatchAdd("*0x0884,x","PROTSTART");
    GEL_WatchAdd("*0x0885,x","PROTRANGE");
}
/********************************************************************/
/* DMA Registers                                                    */
/********************************************************************/
menuitem "Watch DMA Registers";

hotmenu All_DMA_Regs()
{
    GEL_WatchAdd("*0x1000,x","DMACTRL");
    GEL_WatchAdd("*0x1001,x","DEBUGCTRL");
    GEL_WatchAdd("*0x1002,x","REVISION");
    GEL_WatchAdd("*0x1004,x","PRIORITYCTRL1");
    GEL_WatchAdd("*0x1006,x","PRIORITYSTAT");

    GEL_WatchAdd("*0x1020,x","DMA Ch1 MODE");
    GEL_WatchAdd("*0x1021,x","DMA Ch1 CONTROL");
    GEL_WatchAdd("*0x1022,x","DMA Ch1 BURST_SIZE");
    GEL_WatchAdd("*0x1023,x","DMA Ch1 BURST_COUNT");
    GEL_WatchAdd("*0x1024,x","DMA Ch1 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1025,x","DMA Ch1 DST_BURST_STEP");
    GEL_WatchAdd("*0x1026,x","DMA Ch1 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1027,x","DMA Ch1 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1028,x","DMA Ch1 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1029,x","DMA Ch1 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x102A,x","DMA Ch1 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x102B,x","DMA Ch1 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x102C,x","DMA Ch1 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x102D,x","DMA Ch1 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x102E,x","DMA Ch1 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x102F,x","DMA Ch1 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1030,x","DMA Ch1 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1032,x","DMA Ch1 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1034,x","DMA Ch1 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1036,x","DMA Ch1 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1038,x","DMA Ch1 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x103A,x","DMA Ch1 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x103C,x","DMA Ch1 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x103E,x","DMA Ch1 DST_ADDR_ACTIVE");

    GEL_WatchAdd("*0x1040,x","DMA Ch2 MODE");
    GEL_WatchAdd("*0x1041,x","DMA Ch2 CONTROL");
    GEL_WatchAdd("*0x1042,x","DMA Ch2 BURST_SIZE");
    GEL_WatchAdd("*0x1043,x","DMA Ch2 BURST_COUNT");
    GEL_WatchAdd("*0x1044,x","DMA Ch2 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1045,x","DMA Ch2 DST_BURST_STEP");
    GEL_WatchAdd("*0x1046,x","DMA Ch2 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1047,x","DMA Ch2 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1048,x","DMA Ch2 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1049,x","DMA Ch2 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x104A,x","DMA Ch2 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x104B,x","DMA Ch2 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x104C,x","DMA Ch2 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x104D,x","DMA Ch2 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x104E,x","DMA Ch2 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x104F,x","DMA Ch2 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1050,x","DMA Ch2 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1052,x","DMA Ch2 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1054,x","DMA Ch2 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1056,x","DMA Ch2 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1058,x","DMA Ch2 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x105A,x","DMA Ch2 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x105C,x","DMA Ch2 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x105E,x","DMA Ch2 DST_ADDR_ACTIVE");

    GEL_WatchAdd("*0x1060,x","DMA Ch3 MODE");
    GEL_WatchAdd("*0x1061,x","DMA Ch3 CONTROL");
    GEL_WatchAdd("*0x1062,x","DMA Ch3 BURST_SIZE");
    GEL_WatchAdd("*0x1063,x","DMA Ch3 BURST_COUNT");
    GEL_WatchAdd("*0x1064,x","DMA Ch3 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1065,x","DMA Ch3 DST_BURST_STEP");
    GEL_WatchAdd("*0x1066,x","DMA Ch3 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1067,x","DMA Ch3 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1068,x","DMA Ch3 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1069,x","DMA Ch3 DST_TRANSFER_STEP");
    GEL_WatchAdd("*0x106A,x","DMA Ch3 SRC_WRAP_SIZE");
    GEL_WatchAdd("*0x106B,x","DMA Ch3 SRC_WRAP_COUNT");
    GEL_WatchAdd("*0x106C,x","DMA Ch3 SRC_WRAP_STEP");
    GEL_WatchAdd("*0x106D,x","DMA Ch3 DST_WRAP_SIZE");
    GEL_WatchAdd("*0x106E,x","DMA Ch3 DST_WRAP_COUNT");
    GEL_WatchAdd("*0x106F,x","DMA Ch3 DST_WRAP_STEP");
    GEL_WatchAdd("*(long *)0x1070,x","DMA Ch3 SRC_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1072,x","DMA Ch3 SRC_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x1074,x","DMA Ch3 SRC_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1076,x","DMA Ch3 SRC_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x1078,x","DMA Ch3 DST_BEG_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x107A,x","DMA Ch3 DST_ADDR_SHDW");
    GEL_WatchAdd("*(long *)0x107C,x","DMA Ch3 DST_BEG_ADDR_ACTIVE");
    GEL_WatchAdd("*(long *)0x107E,x","DMA Ch3 DST_ADDR_ACTIVE");

    GEL_WatchAdd("*0x1080,x","DMA Ch4 MODE");
    GEL_WatchAdd("*0x1081,x","DMA Ch4 CONTROL");
    GEL_WatchAdd("*0x1082,x","DMA Ch4 BURST_SIZE");
    GEL_WatchAdd("*0x1083,x","DMA Ch4 BURST_COUNT");
    GEL_WatchAdd("*0x1084,x","DMA Ch4 SRC_BURST_STEP");
    GEL_WatchAdd("*0x1085,x","DMA Ch4 DST_BURST_STEP");
    GEL_WatchAdd("*0x1086,x","DMA Ch4 TRANSFER_SIZE");
    GEL_WatchAdd("*0x1087,x","DMA Ch4 TRANSFER_COUNT");
    GEL_WatchAdd("*0x1088,x","DMA Ch4 SRC_TRANSFER_STEP");
    GEL_WatchAdd("*0x1089,x","DMA Ch4 DST_TRANSFER_STEP");