example_2833xda.gel

TMS32028335 的一些例程

}
hotmenu C24x_Mode()
{
    ST1 = ST1 | 0x0100;         /*   AMODE = 1  */
    ST1 = ST1 | 0x0200;         /* OBJMODE = 1  */
}
hotmenu C27x_Mode()
{
    ST1 = ST1 & (~0x0100);      /*   AMODE = 0  */
    ST1 = ST1 & (~0x0200);      /* OBJMODE = 0  */
}


/********************************************************************/
/*                            PLL Ratios                            */
/*                                                                  */
/* The following table describes the PLL clocking ratios (0..10)    */                            
/*                                                                  */
/*   Ratio        CLKIN         Description                         */
/*   -----    --------------    ------------                        */
/*     0      OSCCLK/2          PLL bypassed                        */
/*     1      (OSCCLK * 1)/2    15 Mhz for 30 Mhz CLKIN             */
/*     2      (OSCCLK * 2)/2    30 Mhz for 30 Mhz CLKIN             */
/*     3      (OSCCLK * 3)/2    45 Mhz for 30 Mhz CLKIN             */
/*     4      (OSCCLK * 4)/2    60 Mhz for 30 Mhz CLKIN             */
/*     5      (OSCCLK * 5)/2    75 Mhz for 30 Mhz CLKIN             */
/*     6      (OSCCLK * 6)/2    90 Mhz for 30 Mhz CLKIN             */
/*     7      (OSCCLK * 7)/2    105 Mhz for 30 Mhz CLKIN            */
/*     8      (OSCCLK * 8)/2    120 Mhz for 30 Mhz CLKIN            */
/*     9      (OSCCLK * 9)/2    135 Mhz for 30 Mhz CLKIN            */
/*    10      (OSCCLK * 10)/2   150 Mhz for 30 Mhz CLKIN            */
/********************************************************************/
menuitem "Set PLL Ratio";

hotmenu Bypass()
{
    DIVSEL_div2();     /* DIVSEL = 1/2                      */
    *0x7021 = 0;       /* CLKIN = OSCCLK/2, PLL is bypassed */
    PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 1;      /* CLKIN = (OSCCLK * 1)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 2;      /* CLKIN = (OSCCLK * 2)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 3;      /* CLKIN = (OSCCLK * 3)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 4;      /* CLKIN = (OSCCLK * 4)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 5;      /* CLKIN = (OSCCLK * 5)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 6;      /* CLKIN = (OSCCLK * 6)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 7;      /* CLKIN = (OSCCLK * 7)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 8;      /* CLKIN = (OSCCLK * 8)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 9;      /* CLKIN = (OSCCLK * 9)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_2()
{
    DIVSEL_div2();    /* DIVSEL = 1/2           */
    *0x7021 = 10;     /* CLKIN = (OSCCLK * 10)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x1_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 1;      /* CLKIN = (OSCCLK * 1)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x2_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 2;      /* CLKIN = (OSCCLK * 2)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x3_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 3;      /* CLKIN = (OSCCLK * 3)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x4_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 4;      /* CLKIN = (OSCCLK * 4)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x5_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 5;      /* CLKIN = (OSCCLK * 5)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x6_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 6;      /* CLKIN = (OSCCLK * 6)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x7_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 7;      /* CLKIN = (OSCCLK * 7)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x8_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 8;      /* CLKIN = (OSCCLK * 8)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x9_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 9;      /* CLKIN = (OSCCLK * 9)/2 */
    PLL_Wait();
}
hotmenu OSCCLK_x10_divided_by_1()
{
    DIVSEL_div1();    /* DIVSEL = 1/1           */
    *0x7021 = 10;     /* CLKIN = (OSCCLK * 10)/2 */
    PLL_Wait();
}



/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default.  Switch it to 1/2  */
/********************************************************************/

DIVSEL_div2()
{
    int temp;
    int PLLSTS;

    PLLSTS = 0x7011;

    temp  = *PLLSTS; 
    temp &=  0xFE7F;   /* Clear bits 7 & 8 */
    temp |= 2 << 7;    /* Set bit 8        */
    *PLLSTS = temp;    /* Switch to 1/2    */
}



/********************************************************************/
/* For F2833x devices, DIVSEL is 1/4 by default.  Switch it to /1   */
/********************************************************************/

DIVSEL_div1()
{
    int temp;
    int PLLSTS;

    PLLSTS = 0x7011;
    
    DIVSEL_div2();     /* First switch DIVSEL to 1/2 and wait */
    wait();  
    temp  = *PLLSTS; 
    temp |= 3 << 7;    /* Set bits 7 & 8   */
    *PLLSTS = temp;    /* Switch to 1/2    */
}

wait()
{
    int delay = 0;
    for (delay = 0; delay <= 5; delay ++)
    {}
}

/********************************************************************/
/* For F2833x devices, check the PLLOCKS bit for PLL lock.          */
/********************************************************************/
PLL_Wait()
{
    int PLLSTS;
    int delay = 0;

    PLLSTS = 0x7011;
    
    
    while ( ( (unsigned int)*PLLSTS & 0x0001) != 0x0001)
    {
        delay++;
        GEL_TextOut("Waiting for PLL Lock, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
    }
    GEL_TextOut("\nPLL lock complete, PLLSTS = %x\n",,,,,(unsigned int)*PLLSTS);
}

/********************************************************************/
/* Load the ADC Calibration values from TI OTP                      */
/********************************************************************/
menuitem "ADC Calibration"
hotmenu ADC_Cal()
{
    /* Perform dummy reads of the password locations */
    XAR0 = *0x33FFF8;
    XAR0 = *0x33FFF9;
    XAR0 = *0x33FFFA;
    XAR0 = *0x33FFFB;
    XAR0 = *0x33FFFC;
    XAR0 = *0x33FFFD;
    XAR0 = *0x33FFFE;
    XAR0 = *0x33FFFF;

    
    if(((*0x0AEF) & 0x0001) == 0)
    {
        XAR0 = *0x701C;
        *0x701C |= 0x0008;  
	*0x711C = *0x380083;
        *0x711D = *0x380085;
        *0x701C = XAR0;
	XAR0 = 0;
        GEL_TextOut("\nADC Calibration complete");
       
    } 
    else
    {
        GEL_TextOut("\nADC Calibration not complete, device is secure"); 
    }
}





/********************************************************************/
/* The below are used to display the symbolic names of the F28335   */
/* memory mapped registers in the watch window. To view these       */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to   */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/

/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu __() {}

/********************************************************************/
/* A/D Converter Registers                                          */
/********************************************************************/
menuitem "Watch ADC Registers";

hotmenu All_ADC_Regs()
{
    GEL_WatchAdd("*0x7100,x","ADCTRL1");
    GEL_WatchAdd("*0x7101,x","ADCTRL2");
    GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
    GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
    GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
    GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
    GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
    GEL_WatchAdd("*0x7107,x","ADCASEQSR");
    GEL_WatchAdd("*0x7108,x","ADCRESULT0");
    GEL_WatchAdd("*0x7109,x","ADCRESULT1");
    GEL_WatchAdd("*0x710A,x","ADCRESULT2");
    GEL_WatchAdd("*0x710B,x","ADCRESULT3");
    GEL_WatchAdd("*0x710C,x","ADCRESULT4");
    GEL_WatchAdd("*0x710D,x","ADCRESULT5");
    GEL_WatchAdd("*0x710E,x","ADCRESULT6");
    GEL_WatchAdd("*0x710F,x","ADCRESULT7");
    GEL_WatchAdd("*0x7110,x","ADCRESULT8");
    GEL_WatchAdd("*0x7111,x","ADCRESULT9");
    GEL_WatchAdd("*0x7112,x","ADCRESULT10");
    GEL_WatchAdd("*0x7113,x","ADCRESULT11");
    GEL_WatchAdd("*0x7114,x","ADCRESULT12");
    GEL_WatchAdd("*0x7115,x","ADCRESULT13");
    GEL_WatchAdd("*0x7116,x","ADCRESULT14");
    GEL_WatchAdd("*0x7117,x","ADCRESULT15");
    GEL_WatchAdd("*0x7118,x","ADCTRL3");
    GEL_WatchAdd("*0x7119,x","ADCST");
    GEL_WatchAdd("*0x711C,x","ADCREFSEL");