📄 dsp2833x_dma.c
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EDIS;
}
// This function starts DMA Channel 3.
void StartDMACH3(void)
{
EALLOW;
DmaRegs.CH3.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH4.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH4.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH4.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH4.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH4.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH4.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH4.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx4 = 1; // Enable DMA CH4 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 4.
void StartDMACH4(void)
{
EALLOW;
DmaRegs.CH4.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH5.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH5.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH5.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH5.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH5.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH5.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH5.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx5 = 1; // Enable DMA CH5 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 5.
void StartDMACH5(void)
{
EALLOW;
DmaRegs.CH5.CONTROL.bit.RUN = 1;
EDIS;
}
void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source)
{
EALLOW;
// Set up SOURCE address:
DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning of source buffer
DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source;
// Set up DESTINATION address:
DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning of destination buffer
DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest;
EDIS;
}
void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep)
{
EALLOW;
// Set up BURST registers:
DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in a burst
DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between each word x-ferred
DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each word x-ferred
EDIS;
}
void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep)
{
EALLOW;
// Set up TRANSFER registers:
DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, DMA interrupt will occur after completed transfer
DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when WRAP occurs
DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when WRAP occurs
EDIS;
}
void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep)
{
EALLOW;
// Set up WRAP registers:
DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts
DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap
DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N bursts
DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap
EDIS;
}
void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte)
{
EALLOW;
// Set up MODE Register:
DmaRegs.CH6.MODE.bit.PERINTSEL = persel; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH6.MODE.bit.PERINTE = perinte; // Peripheral interrupt enable
DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; // Oneshot enable
DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; // Continous enable
DmaRegs.CH6.MODE.bit.SYNCE = synce; // Peripheral sync enable/disable
DmaRegs.CH6.MODE.bit.SYNCSEL = syncsel; // Sync effects source or destination
DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; // Enable/disable the overflow interrupt
DmaRegs.CH6.MODE.bit.DATASIZE = datasize; // 16-bit/32-bit data size transfers
DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH6.MODE.bit.CHINTE = chinte; // Channel Interrupt to CPU enable
// Clear any spurious flags:
DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH6.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
PieCtrlRegs.PIEIER7.bit.INTx6 = 1; // Enable DMA CH6 interrupt in PIE
EDIS;
}
// This function starts DMA Channel 6.
void StartDMACH6(void)
{
EALLOW;
DmaRegs.CH6.CONTROL.bit.RUN = 1;
EDIS;
}
//===========================================================================
// No more.
//===========================================================================
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