my.bld

来自「TMS3205402Verilog HDL源码」· BLD 代码 · 共 22 行

Release 7.1i ngdbuild H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500xl my.ngc my.ngd 

Reading NGO file 'D:/cpld/my.ngc' ...

Applying constraints in "top.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 62964 kilobytes

Writing NGD file "my.ngd" ...

Writing NGDBUILD log file "my.bld"...