emac_init.c

TMS320DM6446平台下

/**
*    EMAC - Peripheral setup code
*
*    @date         7/21/2004
*    @author        Magdalena Iovescu
*
**/

#include "emac.h"

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  EMAC/MDIO init                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void emac_init( )
{
    Uint32 i;
    Uint32 value;
    Uint16 phy_ctrl_reg;

    volatile Uint32* pRegAddr = 0;
    /* ---------------------------------------------------------------- *
     *                                                                  *
     *  Reset Ethernet                                                  *
     *                                                                  *
     * ---------------------------------------------------------------- */

    EMAC_REGS->SOFTRESET = 1;                           // EMAC Reset
    while ( EMAC_REGS->SOFTRESET != 0 );                // Wait for Reset to finish

    EWRAP_REGS->EWCTL = CSL_FMKT( EWRAP_EWCTL_INTEN, DISABLE );

    for ( i = 0 ; i < 5 ; i++ )
        value = EWRAP_REGS->EWCTL;

    /* ---------------------------------------------------------------- *
     *                                                                  *
     *  Init PHY / MDIO                                                 *
     *                                                                  *
     * ---------------------------------------------------------------- */
    MDIO_REGS->CONTROL = 0x40000001;                    // Enable MII interface

    PHYREG_read( 2, ACTIVEPHY );                        // Read Phy Id 1

    PHYREG_waitResults( value );                        // Wait for Results

    phy_ctrl_reg = 0
        | ( 0 << 15 )   // Reset
        | ( 0 << 14 )   // Loopback
        | ( 0 << 13 )   // Speed Selection
        | ( 0 << 12 )   // Auto-Negotiation Enable
        | ( 0 << 11 )   // Power-Down
        | ( 0 << 10 )   // Isolate
        | ( 0 << 9 )    // Restart Auto-Negotiation
        | ( 0 << 8 )    // Duplex Mode
        | ( 0 << 7 )    // Collision Test
        | ( 0 << 6 )    // Speed Selection
       ;

    PHYREG_write( phy_ctrl_reg, ACTIVEPHY, 0x0000 );    // Set Control Reg
    PHYREG_wait( );

    /* ---------------------------------------------------------------- *
     *                                                                  *
     *  Setup EMAC                                                      *
     *                                                                  *
     * ---------------------------------------------------------------- */

    /*
     *  Configure RX DMA for operation
     */

    /* Setup device receive MAC addresses for channels 0-7 */
    EMAC_REGS->MACINDEX  = 0x00;
    EMAC_REGS->MACADDRHI = 0x03020100;  /* Needs to be written only the first time */
    EMAC_REGS->MACADDRLO = 0x0504;

    EMAC_REGS->MACINDEX  = 0x01;
    EMAC_REGS->MACADDRLO = 0x1504;

    EMAC_REGS->MACINDEX  = 0x02;
    EMAC_REGS->MACADDRLO = 0x2504;

    EMAC_REGS->MACINDEX  = 0x03;
    EMAC_REGS->MACADDRLO = 0x3504;

    EMAC_REGS->MACINDEX  = 0x04;
    EMAC_REGS->MACADDRLO = 0x4504;

    EMAC_REGS->MACINDEX  = 0x05;
    EMAC_REGS->MACADDRLO = 0x5504;

    EMAC_REGS->MACINDEX  = 0x06;
    EMAC_REGS->MACADDRLO = 0x6504;

    EMAC_REGS->MACINDEX  = 0x07;
    EMAC_REGS->MACADDRLO = 0x7504;

    /* Initialize Rx_HDP registers to zero */
    pRegAddr = &EMAC_REGS->RX0HDP;
    for ( i = 0 ; i < 8 ; i++ )
        *pRegAddr++ = 0;

    /*
     *  While GMIIEN is clear in MACCONTROL, we can write directly to
     *  the statistics registers ( there are "NUM_STAT_REGS" of them ).
     */
    pRegAddr = &EMAC_REGS->RXGOODFRAMES;
    for ( i = 0 ; i < NUM_STAT_REGS ; i++ )
        *pRegAddr++ = 0;

    /* No multicast addressing */
    EMAC_REGS->MACHASH1 = 0;
    EMAC_REGS->MACHASH2 = 0;



    /*
     *  Initialize Rx_FreeBuffer, Rx_FlowThresh, and Rx_FilterLowThresh 
     *  if flow control is to be enabled 
     */

    /* Enable RX channel interrupts ( set mask bits ) */
    EMAC_REGS->RXINTMASKSET = 0xFF;

    /* Enable fullduplex and GMII */
    EMAC_REGS->MACCONTROL = CSL_FMKT( EMAC_MACCONTROL_FULLDUPLEX, ENABLE ) 
                          | CSL_FMKT( EMAC_MACCONTROL_GMIIEN, ENABLE );

    /*
     * For us buffer offset will always be zero
     * valid data always begins on the 1st byte of the buffer 
     */
    EMAC_REGS->RXBUFFEROFFSET = 0;

    /* Enable RX DMA controller */
    CSL_FINST( EMAC_REGS->RXCONTROL, EMAC_RXCONTROL_RXEN, ENABLE );

    /* Reset RX ( M )ulticast ( B )roadcast ( P )romiscuous Enable register */
    EMAC_REGS->RXMBPENABLE = 0;

    /* Enable Unicast RX on channel 0-7 */
    EMAC_REGS->RXUNICASTSET = 0xFF;




    /* Configure TX DMA for operation */



    /* Setup MAC source address - used for pause frames */
    EMAC_REGS->MACSRCADDRLO = 0x03020100;   /* bytes 0, 1 */
    EMAC_REGS->MACSRCADDRHI = 0x0405;       /* bytes 2-5 - channel 0 ??? */

    /* Initialize HDPs registers to zero */
    pRegAddr = &EMAC_REGS->TX0HDP;
    for ( i = 0 ; i < 8 ; i++ )
        *pRegAddr++ = 0;

    /* Enable TX channel interrupts ( set mask bits ) */
    EMAC_REGS->TXINTMASKSET = 0xFF;

    /* Cfg bits in MACCONTROL */
    /* May want to enable TX flow control - TXFLOWEN bit in MACCONTROL */
    /* Setup transmit channels buffer descriptors in host memory */

    /* Enable TX operation */
    CSL_FINST( EMAC_REGS->TXCONTROL, EMAC_TXCONTROL_TXEN, ENABLE );

    /* Enable Host Erorr and Statistics interrupts */
    EMAC_REGS->MACINTMASKSET = CSL_FMK( EMAC_MACINTMASKSET_HOSTERRINTMASK, 1 )
                             | CSL_FMK( EMAC_MACINTMASKSET_STATINTMASK, 1 );
}