arm_intvect_emif.asm

TMS320DM6446平台下

;/*******************************************************************/
;/*                   Davinci evaluation SW                         */
;/*                                                                 */
;/*                              source: interrupt vectors          */
;/*******************************************************************/

    .state32
    .global     _reset_vector
    .global     _undef_vector
    .global     _swi_vector
    .global     _pref_abort_vector
    .global     _data_abort_vector
    .global     _c_intDaVinci
;   .global     _irq_vector
;   .global     _fiq_vector

    .sect       ".intvect"
    .if SIM
    b           _undef_reset_dummy
    .else
    b $
    .endif
    b           _undef_vector_dummy
    b           _swi_vector_dummy
    b           _pref_abort_vector_dummy
    b           _data_abort_vector_dummy
    b           $           ;reserved area
    NOP         ; Branch to irq_vector
    NOP         ; Branch to fiq_vector
_undef_reset_dummy:
    LDR PC, addr_of_reset_vector
addr_of_reset_vector: .field _c_intDaVinci, 32

_undef_vector_dummy:
    LDR PC, addr_of_undef_vector
addr_of_undef_vector: .field _undef_vector, 32

_swi_vector_dummy:
    LDR PC, addr_of_swi_vector
addr_of_swi_vector: .field _swi_vector, 32


_pref_abort_vector_dummy:
    LDR PC, addr_of_pref_abort_vector
addr_of_pref_abort_vector: .field _pref_abort_vector, 32

_data_abort_vector_dummy:
    LDR PC, addr_of_data_abort_vector
addr_of_data_abort_vector: .field _data_abort_vector, 32

;_irq_vector_dummy:
;   LDR PC, addr_of_irq_vector
;addr_of_irq_vector: .field _irq_vector, 32

;_fiq_vector_dummy:
;   LDR PC, addr_of_fiq_vector
;addr_of_fiq_vector: .field _fiq_vector, 32
; Rev.No.   Date/Time               ECN No.          Modifier        ;
; -------   ---------               -------          --------        ;

; 2         19 Oct 2004 19:10:59    3515             xkeshavm        ;
;                                                                    ;
; Added sim variable to support RTL simulation                       ;
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