📄 aic23_lineout_tone_test.c
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/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* AIC33 Lineout Tone Test for C64xx+
*
*/
#include "davincievm_aic33.h"
/* ------------------------------------------------------------------------ *
* *
* AIC33 Lineout Tone *
* *
* AIC33.MCLK = PLL1705.SCK03 *
* FS = ( AIC33.MCLK * K ) / ( 2048 * P ) *
* *
* *
* For a FS=[44.1 kHz] & MCLK=[33.8688 MHz] *
* : 44.1kHz = ( 33.8688 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 5.3333 *
* *
* *
* For a FS=[48 kHz] & MCLK=[33.8688 MHz] *
* : 48kHz = ( 33.8688 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 5.8049 *
* *
* *
* For a FS=[44.1 kHz] & MCLK=[22.5792 MHz] *
* : 44.1kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 8.0000 *
* *
* *
* For a FS=[48 kHz] & MCLK=[22.5792 MHz] *
* : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 8.7075 *
* *
* ------------------------------------------------------------------------ */
Int16 aic23_lineout_tone_test( )
{
Int16 msec;
AIC33_CodecHandle aic33handle;
AIC33_Config aic33config = {
0x0000, // 0-0 Page Select <- [Page=0]
0xAA00, // 0-1 Software Reset <- [ResetOnly]
0x0000, // 0-2 Codec Sample Rate Select <- [ADC=FS][DAC=FS]
// For: [FS=44.1 kHz][MCLK=33.8688 MHz]
//0x0092, // 0-3 PLL Reg A <- [PLL=ON][P=2][Q=2]
//0x0014, // 0-4 PLL Reg B <- [J=5]
//0x0034, // 0-5 PLL Reg C <- [D=3333]
//0x0014, // 0-6 PLL Reg D <- [D=3333]
//0x008A, // 0-7 Codec Datapath Setup <- [FS=44.1 kHz][LeftDACPlays=left][RightDACPlays=right]
// For: [FS=48 kHz][MCLK=33.8688 MHz]
//0x0092, // 0-3 PLL Reg A <- [PLL=ON][P=2][Q=2]
//0x0014, // 0-4 PLL Reg B <- [J=5]
//0x007D, // 0-5 PLL Reg C <- [D=8049]
//0x0004, // 0-6 PLL Reg D <- [D=8049]
//0x000A, // 0-7 Codec Datapath Setup <- [FS=48 kHz][LeftDACPlays=left][RightDACPlays=right]
// For: [FS=44.1 kHz][MCLK=22.5792 MHz]
//0x0092, // 0-3 PLL Reg A <- [PLL=ON][P=2][Q=2]
//0x0020, // 0-4 PLL Reg B <- [J=8]
//0x0000, // 0-5 PLL Reg C <- [D=0000]
//0x0000, // 0-6 PLL Reg D <- [D=0000]
//0x008A, // 0-7 Codec Datapath Setup <- [FS=44.1 kHz][LeftDACPlays=left][RightDACPlays=right]
// For: [FS=48 kHz][MCLK=22.5792 MHz]
0x0092, // 0-3 PLL Reg A <- [PLL=ON][P=2][Q=2]
0x0020, // 0-4 PLL Reg B <- [J=8]
0x006E, // 0-5 PLL Reg C <- [D=7075]
0x0023, // 0-6 PLL Reg D <- [D=7075]
0x000A, // 0-7 Codec Datapath Setup <- [FS=48 kHz][LeftDACPlays=left][RightDACPlays=right]
0x00C0, // 0-8 Audio Serial Data Reg A <- [BCLK=Master][WCLK=Master][3DEffects=OFF][DigitalMIC=OFF]
0x0000, // 0-9 Audio Serial Data Reg B <- [Mode=I2S][Lenght=16-bit][TransferMode=Continous]
0x0000, // 0-10 Audio Serial Data Reg C <- [DataOffset=0]
0xAA00, // 0-11 Overflow Status Reg <- [ReadOnly]
0x0000, // 0-12 Digital Filter Ctrl Reg <- []
0x0000, // 0-13 Headset Detection Reg A <- [HeadsetDetect=OFF]
0x0000, // 0-14 Headset Detection Reg B <- []
0x0000, // 0-15 Left ADC PGA Gain Ctrl Reg <- [Mute=OFF]
0x0000, // 0-16 Right ADC PGA Gain Ctrl Reg <- [Mute=OFF]
0x00FF, // 0-17 MIC3L/R to Left ADC Ctrl Reg <- [MIC3L=NoConnect][MIC3R=NoConnect]
0x00FF, // 0-18 MIC3L/R to Right ADC Ctrl Reg <- [MIC3L=NoConnect][MIC3R=NoConnect]
0x0004, // 0-19 LINE1L to Left ADC Ctrl Reg <- [LINE1L=SingleEnd][LINE1L=0dBGain][LeftADCPower=ON][SoftStep=OncePerFS]
0x0078, // 0-20 LINE2L to Left ADC Ctrl Reg <- [LINE2L=SingleEnd][LINE2L=NoConnect]
0x0078, // 0-21 LINE1R to Left ADC Ctrl Reg <- [LINE1R=SingleEnd][LINE1R=NoConnect]
0x0004, // 0-22 LINE1R to Right ADC Ctrl Reg <- [LINE1R=SingleEnd][LINE1R=0dBGain][RightADCPower=ON][SoftStep=OncePerFS]
0x0078, // 0-23 LINE2R to Right ADC Ctrl Reg <- [LINE2R=SingleEnd][LINE2R=NoConnect]
0x0078, // 0-24 LINE1L to Right ADC Ctrl Reg <- [LINE1L=SingleEnd][LINE1L=NoConnect]
0x0000, // 0-25 MICBIAS Control Reg <- [Power=OFF]
0x0000, // 0-26 Left AGC Control Reg A <- [LeftAGC=OFF]
0x0000, // 0-27 Left AGC Control Reg B <- []
0x0000, // 0-28 Left AGC Control Reg C <- [LeftHystersis=OFF]
0x0000, // 0-29 Right AGC Control Reg A <- [RightAGC=OFF]
0x0000, // 0-30 Right AGC Control Reg B <- []
0x0000, // 0-31 Right AGC Control Reg C <- [RightHystersis=OFF]
0xAA00, // 0-32 Left AGC Gain Reg <- [ReadOnly]
0xAA00, // 0-33 Right AGC Gain Reg <- [ReadOnly]
0x0000, // 0-34 Left AGC Noise Gate Debounce <- []
0x0000, // 0-35 Right AGC Noise Gate Debounce <- []
0xAA00, // 0-36 ADC Flag Reg <- [ReadOnly]
0x00E0, // 0-37 DAC Power & Output Dvr Ctrl Reg <- [LeftDACPower=ON][RightDACPower=ON][HPLCOM=SingleEnd]
0x0010, // 0-38 High Power Output Dvr Ctrl Reg <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
0xFFFF, // 0-39 Reserved <- [Reserved]
0x0000, // 0-40 Output Stage Ctrl Reg <- []
0x0000, // 0-41 DAC Output Switching Ctrl Reg <- []
0x0000, // 0-42 Output Driver Pop Reduction Reg <- []
0x0000, // 0-43 Left DAC Digital Vol Reg <- [LeftDACMute=OFF]
0x0000, // 0-44 Right DAC Digital Vol Reg <- [RightDACMute=OFF]
0x0000, // 0-45 Line2L to HPLOUT Vol Reg <- []
0x0000, // 0-46 PGA_L to HPLOUT Vol Reg <- []
0x0080, // 0-47 DAC_L1 to HPLOUT Vol Reg <- [Routed]
0x0000, // 0-48 LINE2R to HPLOUT Vol Reg <- []
0x0000, // 0-49 PGA_R to HPLOUT Vol Reg <- []
0x0000, // 0-50 DAC_R1 to HPLOUT Vol Reg <- []
0x0009, // 0-51 HPLOUT Output Reg <- [Mute=OFF][Power=ON]
0x0000, // 0-52 LINE2L to HPLCOM Vol Reg <- []
0x0000, // 0-53 PGA_L to HPLCOM Vol Reg <- []
0x0000, // 0-54 DAC_L1 to HPLCOM Vol Reg <- []
0x0000, // 0-55 LINE2R to HPLCOM Vol Reg <- []
0x0000, // 0-56 PGA_R to HPLCOM Vol Reg <- []
0x0000, // 0-57 DAC_R1 to HPLCOM Vol Reg <- []
0x0000, // 0-58 HPLCOM Output Reg <- []
0x0000, // 0-59 LINE2L to HPROUT Vol Reg <- []
0x0000, // 0-60 PGA_L to HPROUT Vol Reg <- []
0x0000, // 0-61 DAC_L1 to HPROUT Vol Reg <- []
0x0000, // 0-62 LINE2R to HPROUT Vol Reg <- []
0x0000, // 0-63 PGA_R to HPROUT Vol Reg <- []
0x0080, // 0-64 DAC_R1 to HPROUT Vol Reg <- [Routed]
0x0009, // 0-65 HPROUT Output Reg <- [Mute=OFF][Power=ON]
0x0000, // 0-66 LINE2L to HPRCOM Vol Reg <- []
0x0000, // 0-67 PGA_L to HPRCOM Vol Reg <- []
0x0000, // 0-68 DAC_L1 to HPRCOM Vol Reg <- []
0x0000, // 0-69 LINE2R to HPRCOM Vol Reg <- []
0x0000, // 0-70 PGA_R to HPRCOM Vol Reg <- []
0x0000, // 0-71 DAC_R1 to HPRCOM Vol Reg <- []
0x0000, // 0-72 HPRCOM Output Reg <- []
0x0000, // 0-73 LINE2L to MONO_LOP/M Vol Reg <- []
0x0000, // 0-74 PGA_L to MONO_LOP/M Vol Reg <- []
0x0000, // 0-75 DAC_L1 to MONO_LOP/M Vol Reg <- []
0x0000, // 0-76 LINE2R to MONO_LOP/M Vol Reg <- []
0x0000, // 0-77 PGA_R to MONO_LOP/M Vol Reg <- []
0x0000, // 0-78 DAC_R1 to MONO_LOP/M Vol Reg <- []
0x0000, // 0-79 MONO_LOP/M Output Reg <- []
0x0000, // 0-80 LINE2L to LEFT_LOP/M Vol Reg <- []
0x0000, // 0-81 PGA_L to LEFT_LOP/M Vol Reg <- []
0x0080, // 0-82 DAC_L1 to LEFT_LOP/M Vol Reg <- [Routed]
0x0000, // 0-83 LINE2R to LEFT_LOP/M Vol Reg <- []
0x0000, // 0-84 PGA_R to LEFT_LOP/M Vol Reg <- []
0x0000, // 0-85 DAC_R1 to LEFT_LOP/M Vol Reg <- []
0x0009, // 0-86 LEFT_LOP/M Output Reg <- [Mute=OFF][Power=ON]
0x0000, // 0-87 LINE2L to RIGHT_LOP/M Vol Reg <- []
0x0000, // 0-88 PGA_L to RIGHT_LOP/M Vol Reg <- []
0x0000, // 0-89 DAC_L1 to RIGHT_LOP/M Vol Reg <- []
0x0000, // 0-90 LINE2R to RIGHT_LOP/M Vol Reg <- []
0x0000, // 0-91 PGA_R to RIGHT_LOP/M Vol Reg <- []
0x0080, // 0-92 DAC_R1 to RIGHT_LOP/M Vol Reg <- [Routed]
0x0009, // 0-93 RIGHT_LOP/M Output Reg<- [Mute=OFF][Power=ON]
0xAA00, // 0-94 Module Power Status Reg <- [ReadOnly]
0xAA00, // 0-95 Output Short Circuit Detection <- [ReadOnly]
0xFFFF, // 0-96 Reserved <- [Reserved]
0xFFFF, // 0-97 Reserved <- [Reserved]
0x0000, // 0-98 GPIO1 Control Reg <- []
0x0000, // 0-99 GPIO2 Control Reg <- []
0x0000, // 0-100 Additional GPIO Control Reg A <- []
0x0000 // 0-101 Additional GPIO Control Reg B <- []
};
/* Pre-generated sine wave data, 16-bit signed samples */
Int16 sinetable[48] = {
0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,
0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,
0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,
0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,
0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,
0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c
};
Int16 sample;
aic33handle = DAVINCIEVM_AIC33_openCodec( 0, &aic33config );
/* Loop for 10 seconds */
for ( msec = 0 ; msec < 10000 ; msec++ )
{
for ( sample = 0 ; sample < 48 ; sample++ )
{
/* Send a sample to the left channel */
while ( ! ( DAVINCIEVM_AIC33_write16( aic33handle, sinetable[sample] ) ) );
/* Send a sample to the right channel */
while ( ! ( DAVINCIEVM_AIC33_write16( aic33handle, sinetable[sample] ) ) );
}
}
DAVINCIEVM_AIC33_closeCodec( aic33handle );
return 0;
}
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