sim.v

来自「32位元2進位SIGNED乘法器32位元SIGNED乘法器」· Verilog 代码 · 共 27 行

module sim;

// module Toplevel (dataP, dataA, dataB, clk, start);

reg clk, start;
reg [31:0] dataA, dataB;

wire [63:0] dataP;

Toplevel test(dataP, dataA, dataB, clk, start);

initial
begin
    clk = 1'b0;
    dataA = 0;
    dataB = 0;
    #100 start = 0;
    #100 start=1;
    #100 start=0;
    #100 dataA = -32'sd5; dataB = -32'sb1011;
end 



always #50 clk=~clk;

endmodule