datapath.v

32位元2進位SIGNED乘法器32位元SIGNED乘法器

module MultiplierV102 (dataP, clear, loadA, loadB, dataA, dataB, shift, done, clk, start, PNtest, PNdet, addsign);

//output A0;
output reg [63:0] dataP;
 
input clear, loadA, loadB, shift, done, clk, start, PNtest, PNdet, addsign;
input [31:0] dataA;
input [31:0] dataB;
//reg A0;
reg [31:0] B;
reg [63:0] P;
wire [31:0] P1;
wire [31:0] sumT1, sumT2;
reg pnA, pnB;
//reg [31:0] zzz;

always @ (negedge clk) 
begin
   if (PNtest) begin
       if (pnB) B <= ~B+1;
       if (pnA) P[31:0] <= ~P[31:0] + 1;
end
end

always @ (PNdet & ~clk) if (pnB ^ pnA) P <= ~P+1; 

always @ (posedge clk) 
begin
if (loadB) 
begin
B = dataB; 
pnB <= B[31];
end
end


always @ (posedge clk) 
begin
if (loadA) 
begin
P[31:0] = dataA;
pnA <= P[31];
end
end

assign A0 = P[0];


//assign sumT = A0 ? (P1+B+33'b00000000_00000000_00000000_000000000) :(P1+33'b00000000_00000000_00000000_000000000);

assign sumT1 = P1+B+32'b0000000_00000000_00000000_000000000;
assign sumT2 = P1+32'b0000000_00000000_00000000_000000000;
//assign P[63:31] = A0 ? sumT1 : sumT2;

always @ (negedge clk & ~done & addsign)
begin
    if (A0) P[63:32] <= sumT1;
    else P[63:32] <= sumT2;
   // zzz <= ~B + 1;
end

always @ (posedge clk)
case({shift, done, clear})
    3'b100 : P <= {1'b0, P[63:1]};
    3'b010 : dataP <= P;
    3'b001 : begin
    P <= 64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
    B <= 32'b00000000_00000000_00000000_00000000;
    //P1 = 32'b00000000_00000000_00000000_00000000;
    //sumT1 = 32'b00000000_00000000_00000000_00000000;
    //sumT2 = 32'b00000000_00000000_00000000_00000000;
    end
    //4'b0001 : if (start & P[0]) P[63:32] <= B; 
    default : P <= P;
endcase

assign P1 = P[63:32];


endmodule