toplevel.v

来自「32位元2進位SIGNED乘法器32位元SIGNED乘法器」· Verilog 代码 · 共 20 行

module Toplevel (dataP, dataA, dataB, clk, start);
    
output [63:0] dataP;

input [31:0] dataA, dataB;
input clk, start;

//module MultiplierV102 (dataP, clear, loadA, loadB, dataA, dataB, shift, done, clk, start, PNtest, PNdet, addsign);
  
//module controller (addsign, PNdet, PNtest, clear, loadA, loadB, shift, done, clk, start);
  

wire clear, loadA, loadB, shift, done, PNdet, PNtest, addsign;

MultiplierV102 datapath (dataP, clear, loadA, loadB, dataA, dataB, shift, done, clk, start, PNtest, PNdet, addsign);
controller control (addsign, PNdet, PNtest, clear, loadA, loadB, shift, done, clk, start);


endmodule