simmemandrom.v

来自「簡易MIPS CPU程式碼 此CPU包含 shift add sub and 」· Verilog 代码 · 共 24 行

module Sim;

reg clk, memread, memwrite;
reg [31:0] writedata, address;
wire [31:0] memdata;
memANDrom TTT(memdata, clk, memread, memwrite, writedata, address);

initial
begin
    clk = 1'b0;
    //reset = 1'b0;
    //#100 reset = 1'b1;
    //#100 reset = 1'b0;
    #100 memwrite = 1'b0;
    address = {6'd35, 5'd0, 5'd4, 16'd0};
    writedata = 32'd1;
    memread = 1'b1;
    
end

always #50 clk = ~clk;

endmodule