📄 uart_vfifo.c
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}
else
{
DMA_PUSH(ch,data);
}
}
}
}
else
{
real_count = UART_PutISRBytes(port, Buffaddr, Length, ownerid);
}
/*invoke THRE interrupt*/
//EnableTxIntr(UART_BaseAddr[port]);
return real_count;
#else
return Length;
#endif
}
/************************ISR level**************************************************/
kal_uint32 last_w;
kal_uint32 last_r;
void UART_RecTimeOutHandler(void *parameter)
{
UARTStruct *UARTData=(UARTStruct *)parameter;
kal_uint32 UART_BASE = UART_BaseAddr[UARTData->port_no];
kal_uint16 avail;
kal_uint8 ch;
volatile kal_uint8 tmp;
#ifdef VFIFO_DBG
gUART_RecTimeOutHandler++;
#endif
// clear the timeout interrupt
tmp = DRV_Reg(UART_RXDMA(UART_BASE));
//check if no incomming data ----for future don't remove it.
//if(!(DRV_Reg(UART_RXDMA(UART_BASE))&UART_RXDMA_TIMEOUT))
//return;
// inform the upper layer to check virtual fifo remains data
ch = UARTData->Rx_DMA_Ch;
avail = DMA_GetVFIFO_Avail(ch);
if(avail == 0)
return;
/*TY adds these to expand flexibility 2004/10/15*/
UARTPort[UARTData->port_no].rx_cb(UARTData->port_no);
DMA_DisableINT(ch);
if (UARTData->ESCDet.GuardTime != 0)
{
UARTStruct *UARTData=(UARTStruct *)parameter;
switch(UARTData->Rec_state)
{
case UART_Get3EscChar:
UARTData->Rec_state = UART_RecNormal;
UARTData->EscCount = 0;
break;
case UART_RecNormal:
UARTData->Rec_state = UART_RecNormal;
UARTData->EscCount = 0;
break;
case UART_StartCheckESC:
if(avail>3)
{
UARTData->Rec_state = UART_RecNormal;
UARTData->EscCount = 0;
}
else
{
kal_uint16 i;
kal_uint8 data;
last_w=DRV_Reg32(DMA_WRPTR(ch));
for(i=1;i<(avail+1);i++)
{
last_w--;
if( (last_w) <(kal_uint32) UART_rings->ring[UARTData->port_no].rx_adrs )
last_w=(kal_uint32)UART_rings->ring[UARTData->port_no].rx_adrs+
UART_rings->ring[UARTData->port_no].rx_len-1;
data=DRV_Reg8((last_w));
if(data==UARTData->ESCDet.EscChar)
{
UARTData->EscCount++;
if(UARTData->EscCount == 3)
{
UARTData->Rec_state = UART_Get3EscChar;
}
else if(UARTData->EscCount > 3)
{
UARTData->Rec_state = UART_RecNormal;
UARTData->EscCount = 0;
}
}
else
{
UARTData->Rec_state = UART_RecNormal;
UARTData->EscCount = 0;
}
}
}
break;
default:
break;
}
GPTI_StartItem(UARTData->handle,
(UARTData->ESCDet.GuardTime/10),
UART_Calback,
&UARTPort[UARTData->port_no]);
}
}
// called by DMA ISR while tx fifo is under the threshold
void UART_TrxHandler_VFIFO(void *parameter)
{
UARTStruct *UARTData=(UARTStruct *)parameter;
kal_int16 room;
kal_uint8 ch;
#ifdef VFIFO_DBG
gUART_TrxHandler_VFIFO++;
#endif
ch = UARTData->Tx_DMA_Ch;
room = DMA_GetVFIFO_Roomleft(ch);
if(room == 0)
return;
/* inform the upper layer to send data to vfifo*/
/*TY adds these to expand flexibility 2004/10/15*/
UARTPort[UARTData->port_no].tx_cb(UARTData->port_no);
DMA_DisableINT(ch);
}
// called by DMA ISR while rx vfifo is over the threshold
void UART_RecHandler_VFIFO(void *parameter)
{
UARTStruct *UARTData=(UARTStruct *)parameter;
kal_int16 avail;
kal_uint8 ch;
#ifdef VFIFO_DBG
gUART_RecHandler_VFIFO++;
#endif
ch = UARTData->Rx_DMA_Ch;
avail = DMA_GetVFIFO_Avail(ch);
if(avail == 0)
return;
// inform the upper layer to get data from vfifo
/*TY adds these to expand flexibility 2004/10/15*/
UARTPort[UARTData->port_no].rx_cb(UARTData->port_no);
DMA_DisableINT(ch);
}
void UART_THRE_hdr_VFIFO(UART_PORT port)
{
kal_uint16 avail;
kal_uint32 UART_BASE = UART_BaseAddr[port];
/*check if there is data in ring buffer*/
avail=DMA_GetVFIFO_Avail(UARTPort[port].Tx_DMA_Ch);
if(avail==0)
{
switch(port)
{
case uart_port1:
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_UART1,PDN_UART1);
break;
case uart_port2:
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_UART2,PDN_UART2);
break;
#ifdef __UART3_SUPPORT__
case uart_port3:
#if ( (defined(MT6219))||defined(MT6226M)||(defined(MT6228))|| defined(MT6229)|| (defined(MT6226))|| (defined(MT6227)) )
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_UART3,PDN_UART3);
#endif
break;
#endif /*__UART3_SUPPORT__*/
default:
ASSERT(0);
break;
}
DisableTxIntr(UART_BASE);
}
}
void U_configure_DMA_VFIFO(void)
{
#if defined(MT6218B) || defined(MT6217)
if(UART_rings->not_support_VFIFO==uart_port1)
{
UARTPort[uart_port2].Rx_DMA_Ch=11;//12;
UARTPort[uart_port2].Tx_DMA_Ch=10;//11;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=12;//13;
UARTPort[uart_port3].Tx_DMA_Ch=13;//14;
#endif
UART_VFIFO_support[uart_port1]=KAL_FALSE;
}
else if(UART_rings->not_support_VFIFO==uart_port2)
{
UARTPort[uart_port1].Rx_DMA_Ch=10;//11;
UARTPort[uart_port1].Tx_DMA_Ch=11;//12;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=12;//13;
UARTPort[uart_port3].Tx_DMA_Ch=13;//14;
#endif
UART_VFIFO_support[uart_port2]=KAL_FALSE;
}
else if(UART_rings->not_support_VFIFO==uart_port3)
{
UARTPort[uart_port1].Rx_DMA_Ch=10;//11;
UARTPort[uart_port1].Tx_DMA_Ch=12;//13;
UARTPort[uart_port2].Rx_DMA_Ch=11;//12;
UARTPort[uart_port2].Tx_DMA_Ch=13;//14;
#ifdef __UART3_SUPPORT__
UART_VFIFO_support[uart_port3]=KAL_FALSE;
#endif
}
else
{
UART_VFIFO_support[uart_port2]=KAL_FALSE;
UARTPort[uart_port1].Rx_DMA_Ch=10;//11;
UARTPort[uart_port1].Tx_DMA_Ch=11;//12;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=12;//13;
UARTPort[uart_port3].Tx_DMA_Ch=13;//14;
#endif
}
#else
if(UART_rings->not_support_VFIFO==uart_port1)
{
UARTPort[uart_port2].Rx_DMA_Ch=12;
UARTPort[uart_port2].Tx_DMA_Ch=11;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=13;
UARTPort[uart_port3].Tx_DMA_Ch=14;
#endif
UART_VFIFO_support[uart_port1]=KAL_FALSE;
}
else if(UART_rings->not_support_VFIFO==uart_port2)
{
UARTPort[uart_port1].Rx_DMA_Ch=11;
UARTPort[uart_port1].Tx_DMA_Ch=12;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=13;
UARTPort[uart_port3].Tx_DMA_Ch=14;
#endif
UART_VFIFO_support[uart_port2]=KAL_FALSE;
}
else if(UART_rings->not_support_VFIFO==uart_port3)
{
UARTPort[uart_port1].Rx_DMA_Ch=11;
UARTPort[uart_port1].Tx_DMA_Ch=13;
UARTPort[uart_port2].Rx_DMA_Ch=12;
UARTPort[uart_port2].Tx_DMA_Ch=14;
#ifdef __UART3_SUPPORT__
UART_VFIFO_support[uart_port3]=KAL_FALSE;
#endif
}
else
{
UART_VFIFO_support[uart_port2]=KAL_FALSE;
UARTPort[uart_port1].Rx_DMA_Ch=11;
UARTPort[uart_port1].Tx_DMA_Ch=12;
#ifdef __UART3_SUPPORT__
UARTPort[uart_port3].Rx_DMA_Ch=13;
UARTPort[uart_port3].Tx_DMA_Ch=14;
#endif
}
#endif
}
#if 1
extern kal_bool U_Open(UART_PORT port, module_type owner);
extern void U_Close(UART_PORT port);
extern void U_Purge(UART_PORT port, UART_buffer dir);
extern void U_SetOwner (UART_PORT port, kal_uint8 owner);
extern void U_SetFlowCtrl(UART_PORT port, kal_bool XON);
extern void U_CtrlDCD(UART_PORT port, IO_level SDCD);
extern void U_ConfigEscape (UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime);
extern void U_SetDCBConfig(UART_PORT port, UARTDCBStruct *UART_Config);
extern void U_CtrlBreak(UART_PORT port, IO_level SBREAK);
extern void U_ClrRxBuffer(UART_PORT port);
extern void U_ClrTxBuffer(UART_PORT port);
extern void U_SetBaudRate(UART_PORT port, UART_baudrate baudrate);
extern module_type U_GetOwnerID(UART_PORT port);
extern void U_SetAutoBaud_Div(UART_PORT port);
extern void U_Register_TX_cb(UART_PORT port, module_type owner, UART_TX_FUNC func);
extern void U_Register_RX_cb(UART_PORT port, module_type owner, UART_RX_FUNC func);
extern void U_PutUARTBytes(UART_PORT port, kal_uint8 *data,kal_uint16 len);
extern void U_ReadDCBConfig (UART_PORT port, UARTDCBStruct *DCB);
extern void U_CtrlRI (UART_PORT port, IO_level SRI); /*NULL for DCE*/
extern void U_CtrlDTR (UART_PORT port, IO_level SDTR);
extern void U_ReadHWStatus(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
// uart dispatch funtion table
UartDriver_strcut UartDriver_VFIFO=
{
U_Open,
U_Close,
U_GetBytes_VFIFO,
U_PutBytes_VFIFO,
U_GetBytesAvail_VFIFO,
U_GetTxRoomLeft_VFIFO,
U_PutISRBytes_VFIFO,
U_GetTxISRRoomLeft_VFIFO,
U_Purge,
U_SetOwner,
U_SetFlowCtrl,
U_ConfigEscape,
U_SetDCBConfig,
U_CtrlDCD,
U_CtrlBreak,
U_ClrRxBuffer,
U_ClrTxBuffer,
U_SetBaudRate,
U_SendISRData_VFIFO,
U_SendData_VFIFO,
U_GetOwnerID,
U_SetAutoBaud_Div,
/*TY adds these to expand flexibility 2004/10/15*/
U_Register_TX_cb,
U_Register_RX_cb,
/*TY adds these to let virtual COM port can retrive exception log 2005/3/8*/
U_GetUARTByte_VFIFO,
U_PutUARTByte_VFIFO,
U_PutUARTBytes,
/*for virtual com port to return DCB configuration*/
U_ReadDCBConfig,
U_CtrlRI,
U_CtrlDTR,
U_ReadHWStatus
};
#endif
#endif //__DMA_UART_VIRTUAL_FIFO__
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