uart.c

uart全功能实现.实现如下函数: U_Open, U_Close, U_GetBytes, U_PutBytes, U_GetBytesAvail, U_GetTxRoomL

/* under construction !*/
/* under construction !*/
/* under construction !*/
#ifdef __UART3_SUPPORT__
/* under construction !*/
            #if ( (!defined(MT6217)) && (!defined(MT6218B)) )                        
/* under construction !*/
            #endif
/* under construction !*/
#endif   /*__UART3_SUPPORT__*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif

   kal_mem_cpy( &UARTPort[port].DCB, UART_Config, sizeof(UARTDCBStruct) );

   savedMask = SaveAndSetIRQMask();
   DRV_WriteReg(UART_IER(UART_BASE),IER);
   RestoreIRQMask(savedMask);
}

void U_ReadDCBConfig (UART_PORT port, UARTDCBStruct *DCB)
{
   kal_mem_cpy( DCB, &UARTPort[port].DCB, sizeof(UARTDCBStruct) );
}

void UART_loopback(UART_PORT port)
{
  kal_uint16 tmp;
  kal_uint32 UART_BASE = UART_BaseAddr[port];
  /* Enable Loop Back test!! */
  tmp = DRV_Reg(UART_MCR(UART_BASE));
  tmp |= UART_MCR_LOOPB;
  DRV_WriteReg(UART_MCR(UART_BASE),tmp);
}

void UART_HWInit(UART_PORT port)
{
   kal_uint8 tmp;
   UARTDCBStruct *DCBdefault;
   UARTDCBStruct  UART_DefaultConfig =
   {
      UART_BAUD_115200,    /* baud; */
      len_8,               /* dataBits; */
      sb_1,                /*stopBits; */
      pa_none,             /* parity; */
      fc_none,             /*no flow control*/
      0x11,                /* xonChar; */
      0x13,                /* xoffChar; */
      KAL_FALSE
   };
   kal_uint32 UART_BASE = UART_BaseAddr[port];
      
#ifdef __ROMSA_SUPPORT__
   /*for MCUROM*/
   #ifdef DRV_DEBUG
   UART_debug=KAL_TRUE;
   #else
   UART_debug=KAL_FALSE;
   #endif
   #ifdef __DMA_UART_VIRTUAL_FIFO__
   UART_Virtual_FIFO=KAL_TRUE;
   #else
   UART_Virtual_FIFO=KAL_FALSE;
   #endif
#endif
   switch(port)
   {
      case uart_port1:
         DRV_Reg(DRVPDN_CON1) &= ~(DRVPDN_CON1_UART1);
			#ifdef __DMA_UART_VIRTUAL_FIFO__
			if(UART_VFIFO_support[port])
			{
			   DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].rx_adrs, UART_rings->ring[port].rx_len, UARTPort[uart_port1].Rx_DMA_Ch, KAL_FALSE);
		      DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].tx_adrs, UART_rings->ring[port].tx_len, UARTPort[uart_port1].Tx_DMA_Ch, KAL_TRUE);
			   //UARTPort[port].Rx_DMA_Ch = VDMA_UART1RX_CH;
			   //UARTPort[port].Tx_DMA_Ch = VDMA_UART1TX_CH;
			}   
      	#endif
         break;
      case uart_port2:
         DRV_Reg(DRVPDN_CON1) &= ~(DRVPDN_CON1_UART2);
			#ifdef __DMA_UART_VIRTUAL_FIFO__
			if(UART_VFIFO_support[port])
			{
			   DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].rx_adrs, UART_rings->ring[port].rx_len, UARTPort[uart_port2].Rx_DMA_Ch, KAL_FALSE);
		      DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].tx_adrs, UART_rings->ring[port].tx_len, UARTPort[uart_port2].Tx_DMA_Ch, KAL_TRUE);
			   //DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].rx_adrs, UART_rings->ring[port].rx_len, VDMA_UART2RX_CH, KAL_FALSE);
		      //DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].tx_adrs, (UART_rings->ring[port].tx_len /*+UART_rings->ring[port].txisr_len*/), VDMA_UART2TX_CH, KAL_TRUE);		   
			   //UARTPort[port].Rx_DMA_Ch = VDMA_UART2RX_CH;
			   //UARTPort[port].Tx_DMA_Ch = VDMA_UART2TX_CH;
			}   
        #endif
         break;
#ifdef __UART3_SUPPORT__
      case uart_port3:
         #if ( (!defined(MT6217)) && (!defined(MT6218B)) )              
         DRV_Reg(DRVPDN_CON1) &= ~(DRVPDN_CON1_UART3);
         #endif
         #ifdef __DMA_UART_VIRTUAL_FIFO__
         if(UART_VFIFO_support[port])
         {
            DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].rx_adrs, UART_rings->ring[port].rx_len, UARTPort[uart_port3].Rx_DMA_Ch, KAL_FALSE);
		      DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].tx_adrs, UART_rings->ring[port].tx_len, UARTPort[uart_port3].Tx_DMA_Ch, KAL_TRUE);
			   //DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].rx_adrs, UART_rings->ring[port].rx_len, VDMA_UART3RX_CH, KAL_FALSE);
		      //DMA_Vfifo_SetAdrs((kal_uint32)UART_rings->ring[port].tx_adrs, UART_rings->ring[port].tx_len, VDMA_UART3TX_CH, KAL_TRUE);		   
			   //UARTPort[port].Rx_DMA_Ch = VDMA_UART3RX_CH;
			   //UARTPort[port].Tx_DMA_Ch = VDMA_UART3TX_CH;
			}   
         #endif/*__DMA_UART_VIRTUAL_FIFO__*/         
         break;
#endif   /*__UART3_SUPPORT__*/
      default:
         ASSERT(0);
         break;
   }

   DCBdefault = (UARTDCBStruct *)&UART_DefaultConfig;
   /* Setup N81,(UART_WLS_8 | UART_NONE_PARITY | UART_1_STOP) = 0x03 */
   /* BaudRate and autoflowcontrol */
   U_SetDCBConfig(port, DCBdefault);

#ifdef UART_HIGHSPEED_TEST
   DRV_WriteReg(UART_RATE_STEP(UART_BASE),0x01);
   DRV_WriteReg(UART_LCR(UART_BASE),0xbf);
   DRV_WriteReg(UART_DLL(UART_BASE),0x07);
   DRV_WriteReg(UART_LCR(UART_BASE),0x03);
#endif   /*UART_HIGHSPEED_TEST*/
   /* SER_SetConfig((char *)DCBdefault); */

   tmp = DRV_Reg(UART_LSR(UART_BASE));
   tmp = DRV_Reg(UART_MSR(UART_BASE));
   /* DTR , RTS is on, data will be coming,Output2 is high */
   DRV_WriteReg(UART_MCR(UART_BASE),UART_MCR_Normal);
   DRV_WriteReg(UART_IER(UART_BASE),UART_IER_ALLOFF);
   /* Enable UART int. controller */
   /* UART1_IER, enable RDA, RLS, MS , disable THR interrupt */
   /* DRV_WriteReg(UART1_IER,UART_IER_RDA); */
   GPTI_GetHandle(&UARTPort[port].handle);
   UARTPort[port].Rec_state = UART_RecNormal;
   UARTPort[port].port_no = port;

   UARTPort[port].sleep_on_tx = uart_sleep_on_tx_allow;
   UARTPort[port].EnableTX= KAL_TRUE;
   UARTPort[port].power_on= KAL_TRUE;
#if ( (defined(MT6218B))||defined(MT6226M) || (defined(MT6219))|| (defined(MT6217))|| (defined(MT6228))|| (defined(MT6229))|| (defined(MT6226))|| (defined(MT6227)) )
   DRV_WriteReg(UART_SLEEP_EN(UART_BASE),KAL_TRUE);
   #endif
}

kal_bool U_Open(UART_PORT port, module_type owner)
{
   kal_uint32 UART_BASE = UART_BaseAddr[port];
   kal_uint16  MSR;
   kal_uint8 byte;
   kal_uint8 i;
#ifdef MT6208
   kal_uint16 UART_IER_HW_NORMALINTS[MAX_UART_PORT_NUM] = {
      UART1_IER_HW_NORMALINTS,
      UART2_IER_HW_NORMALINTS
   };
   kal_uint16 UART_IER_SW_NORMALINTS[MAX_UART_PORT_NUM] = {
      UART1_IER_SW_NORMALINTS,
      UART2_IER_SW_NORMALINTS
   };
#endif   /*MT6208*/

	if(port == uart_port_null)
		return KAL_FALSE;
		
	#ifdef DRV_DEBUG
	if (uart_initialize[port])
	       return KAL_TRUE;
	else
	       uart_initialize[port] = KAL_TRUE;
	#endif /*DRV_DEBUG*/
	
   if (UARTPort[port].initialized &&
   	(UARTPort[port].ownerid != MOD_UART1_HISR + port))
      return KAL_FALSE;
   UARTPort[port].initialized = KAL_TRUE;
   UARTPort[port].ownerid = owner;
   
	/* initialize the ring buffer according to the owner */
	for(i = 0; i < MAX_UART_PORT_NUM; i++)
	{
		if(UART_rings->ring[i].owerid == owner)
		{
			UARTPort[port].RingBuffers.rx_buffer = UART_rings->ring[i].rx_adrs;
			UARTPort[port].RingBuffers.tx_buffer = UART_rings->ring[i].tx_adrs;
			Buf_init(&(UARTPort[port].Rx_Buffer),(kal_uint8 *)(UARTPort[port].RingBuffers.rx_buffer),(kal_uint16)UART_rings->ring[i].rx_len);
		   Buf_init(&(UARTPort[port].Tx_Buffer),(kal_uint8 *)(UARTPort[port].RingBuffers.tx_buffer),(kal_uint16)UART_rings->ring[i].tx_len);   		  		   
		
			//#ifndef __DMA_UART_VIRTUAL_FIFO__
			if(UART_VFIFO_support[port]==KAL_FALSE)
			{
			UARTPort[port].RingBuffers.txISR_buffer = UART_rings->ring[i].txisr_adrs;
			Buf_init(&(UARTPort[port].Tx_Buffer_ISR),(kal_uint8 *)(UARTPort[port].RingBuffers.txISR_buffer),(kal_uint16)UART_rings->ring[i].txisr_len);						
			}   
		   //#endif // __DMA_UART_VIRTUAL_FIFO__
		   
		   break;
		}
	}
	
	/* the owner is not defined in ring buffer, use default=> ring[0]: com1, ring[1] com2 ... */
	if(i == MAX_UART_PORT_NUM)
	{
	   #if (defined(__MAUI_BASIC__)) && (defined(MONZA)) 
		#ifdef __UART3_SUPPORT__
		EXT_ASSERT((owner == MOD_UART1_HISR ||owner == MOD_UART2_HISR||owner == MOD_UART3_HISR),owner,0,0);			
		#else
		EXT_ASSERT((owner == MOD_UART1_HISR ||owner == MOD_UART2_HISR),owner,0,0);			
		#endif	
		#endif
		
		UARTPort[port].RingBuffers.rx_buffer = UART_rings->ring[port].rx_adrs;
		UARTPort[port].RingBuffers.tx_buffer = UART_rings->ring[port].tx_adrs;
		Buf_init(&(UARTPort[port].Rx_Buffer),(kal_uint8 *)(UARTPort[port].RingBuffers.rx_buffer),(kal_uint16)UART_rings->ring[port].rx_len);
	   Buf_init(&(UARTPort[port].Tx_Buffer),(kal_uint8 *)(UARTPort[port].RingBuffers.tx_buffer),(kal_uint16)UART_rings->ring[port].tx_len);   
		//#ifndef __DMA_UART_VIRTUAL_FIFO__	
		if(UART_VFIFO_support[port]==KAL_FALSE)
		{
		UARTPort[port].RingBuffers.txISR_buffer = UART_rings->ring[port].txisr_adrs;
		Buf_init(&(UARTPort[port].Tx_Buffer_ISR),(kal_uint8 *)(UARTPort[port].RingBuffers.txISR_buffer),(kal_uint16)UART_rings->ring[port].txisr_len);				
	   }
		//#endif	   
	}
      
   MSR = DRV_Reg(UART_MSR(UART_BASE));
   if (MSR & UART_MSR_DSR)
      UARTPort[port].DSR = io_high;
   else
      UARTPort[port].DSR = io_low;

   #ifdef __DMA_UART_VIRTUAL_FIFO__
   if(UART_VFIFO_support[port])
   {
   	/* Rx FIFO trigger = 1, Tx FIFO trigger is 1, FIFO enable and initialized,and using DMA mode 0.*/
   	// while using virtual fifo, dma mode must be set 0!!!
   	DRV_WriteReg(UART_FCR(UART_BASE),UART_VFIFO_DEPTH);
   //#else
   }
   else
   {
   	/* Rx FIFO trigger = 62, Tx FIFO trigger is 16, and FIFO enable. */
   	DRV_WriteReg(UART_FCR(UART_BASE),UART_FCR_Normal);
   }   
   #else
   /* Rx FIFO trigger = 62, Tx FIFO trigger is 16, and FIFO enable. */
   DRV_WriteReg(UART_FCR(UART_BASE),UART_FCR_Normal);
   #endif //__DMA_UART_VIRTUAL_FIFO__

#ifdef MT6208
   if (UARTPort[port].DCB.flowControl == fc_none)
      DRV_WriteReg(UART_IER(UART_BaseAddr[port]),UART_IER_HW_NORMALINTS[port]);
   else
   {
      if (UARTPort[port].DCB.flowControl == fc_hw)
         DRV_WriteReg(UART_IER(UART_BaseAddr[port]),UART_IER_HW_NORMALINTS[port]);
      else
      {
         if (UARTPort[port].DCB.flowControl == fc_sw)
            DRV_WriteReg(UART_IER(UART_BaseAddr[port]),UART_IER_SW_NORMALINTS[port]);
      }
   }
#else /*!MT6208*/
	//#ifdef __DMA_UART_VIRTUAL_FIFO__
	if(UART_VFIFO_support[port])
	{
		#ifdef __DMA_UART_VIRTUAL_FIFO__
		// only turn on receive interrupt
		DRV_WriteReg(UART_IER(UART_BaseAddr[port]),UART_IER_VFIFO);
		DMA_Stop(UARTPort[port].Rx_DMA_Ch);
		DMA_Stop(UARTPort[port].Tx_DMA_Ch);
		DMA_Start(UARTPort[port].Rx_DMA_Ch);
		DMA_Start(UARTPort[port].Tx_DMA_Ch);		
   	DRV_WriteReg(UART_RXDMA(UART_BASE),UART_RXDMA_ON);
   	#else
   	ASSERT(0);/*wrong configuration*/
   	#endif
   }
   else
   {	
	   //#else //__DMA_UART_VIRTUAL_FIFO__
   	if (UARTPort[port].DCB.flowControl == fc_none)
   	   DRV_WriteReg(UART_IER(UART_BaseAddr[port]),IER_HW_NORMALINTS);
   	else
   	{
   	   if (UARTPort[port].DCB.flowControl == fc_hw)
   	      DRV_WriteReg(UART_IER(UART_BaseAddr[port]),IER_HW_NORMALINTS);
   	   else
   	   {
   	      if (UARTPort[port].DCB.flowControl == fc_sw)
   	      {
   	         DRV_WriteReg(UART_IER(UART_BaseAddr[port]),IER_SW_NORMALINTS);                        
   	         if(uart_support_autoescape()==KAL_TRUE)
   	         {
   	            /*For META, Dont use auto escape*/
					   if(stack_query_boot_mode() != FACTORY_BOOT)
					   {
   	               /*For AutoEscape*/
   	               byte = DRV_Reg(UART_LCR(UART_BASE));
   	               // DLAB start */
   	               DRV_WriteReg(UART_LCR(UART_BASE),0xbf);            /* Enchance setting */
   	               DRV_WriteReg(UART_XON1(UART_BaseAddr[port]),0x11);
   	               DRV_WriteReg(UART_XON2(UART_BaseAddr[port]),0x11);
   	               DRV_WriteReg(UART_XOFF1(UART_BaseAddr[port]),0x13);
   	               DRV_WriteReg(UART_XOFF2(UART_BaseAddr[port]),0x13);
   	               #if (!defined(MT6205B)&&!defined(MT6208)&&defined(FPGA)) 
   	               DRV_WriteReg(UART_ESCAPE_DAT(UART_BaseAddr[port]),0x77);
   	               DRV_WriteReg(UART_ESCAPE_EN(UART_BaseAddr[port]),0x1);
   	               #endif
   	               DRV_WriteReg(UART_LCR(UART_BASE),byte);            /* Enchance setting */            
   	            }
   	         }              
   	      }   
   	   }
   	}
   }      
	//#endif //__DMA_UART_VIRTUAL_FIFO__
#endif   /*MT6208*/
    /*For excetpion, we dont need to do the following */
    #ifdef __MTK_TARGET__
    if(INT_QueryExceptionStatus())
      return KAL_TRUE; 
   #endif   

   /* UARTPort[port].callback = FunCallBack; */
   /* UARTPort[port].initialized = KAL_TRUE; */
   /* initializ our ringbuffer,  */
   send_Rxilm[port] = KAL_TRUE;
   if (UARTPort[port].hisr == NULL)
   {
      //UARTPort[port].hisr = kal_create_hisr("UARTx_HISR",1,512,UART_HISR[port],NULL);
      UARTPort[port].hisr=(void*)0x1234;
      if(port==uart_port1)
         DRV_Register_HISR(DRV_UART1_HISR_ID,UART_HISR[port]);
      if(port==uart_port2)
         DRV_Register_HISR(DRV_UART2_HISR_ID,UART_HISR[port]);
      if(port==uart_port3)
         DRV_Register_HISR(DRV_UART3_HISR_ID,UART_HISR[port]);      
   }   

   switch(port)
   {
      case uart_port1:
         UARTPort[port].UART_id = MOD_UART1_HISR;
         IRQ_Register_LISR(IRQ_UART1_CODE, UART1_LISR,"UART1");
         IRQSensitivity(IRQ_UART1_CODE,LEVEL_SENSITIVE);
         if (UARTPort[port].power_on == KAL_TRUE)
            IRQUnmask(IRQ_UART1_CODE);
         break;
      case uart_port2:
         #if ( (defined(MT6218))||defined(MT6226M) || (defined(MT6218B)) || (defined(MT6219)) ||(defined(MT6217))||(defined(MT6228))|| defined(MT6229)|| (defined(MT6226))|| (defined(MT6227)) )
         //#ifndef __DMA_UART_VIRTUAL_FIFO__
         if(UART_VFIFO_support[uart_port2]==KAL_FALSE)
         {
            /*DMA initialize*/
            if (uart2_dmaport == 0)
               uart2_dmaport = DMA_GetChannel(DMA_UART2TX);
            uart2_txmenu.TMOD.burst_mode = 0;
            uart2_txmenu.TMOD.cycle = 0;
            uart2_txmenu.master = DMA_UART2TX;
            uart2_txmenu.addr = NULL;  /*1*/
            uart2_txmenu.WPPT = NULL; /*2*/
            uart2_txmenu.WPTO = NULL;     /*3*/

            uart2_input.type = DMA_HWTX_RINGBUFF;
            uart2_input.size = DMA_BYTE;
            uart2_input.menu = &uart2_txmenu;
            uart2_input.count = 0;       /*4*/
            uart2_input.callback = NULL;   /*5*/
         }   
         //#endif //__DMA_UART_VIRTUAL_FIFO__
         #endif   /*MT6218*/
         UARTPort[port].UART_id = MOD_UART2_HISR;
         IRQ_Register_LISR(IRQ_UART2_CODE, UART2_LISR,"UART2");
         IRQSensitivity(IRQ_UART2_CODE,LEVEL_SENSITIVE);
         if (UARTPort[port].power_on == KAL_TRUE)
            IRQUnmask(IRQ_UART2_CODE);
         break;

#ifdef __UART3_SUPPORT__
      case uart_port3:
         UARTPort[port].UART_id = MOD_UART3_HISR;
         IRQ_Register_LISR(IRQ_UART3_CODE, UART3_LISR,"UART3");
         IRQSensitivity(IRQ_UART3_CODE,LEVEL_SENSITIVE);
         if (UARTPort[port].power_on == KAL_TRUE)
            IRQUnmask(IRQ_UART3_CODE);
         break;
#endif   /*__UART3_SUPPORT__*/
      default:
         ASSERT(0);
         break;
   }
   // enable virtual fifo

   return KAL_TRUE;
}
void U_Purge(UART_PORT port, UART_buffer dir)
{
   kal_uint32 UART_BASE = UART_BaseAddr[port];

   /* Rx FIFO trigger = 62, Tx FIFO trigger is 16, and FIFO enable. */
   if (dir == RX_BUF)
      DRV_WriteReg(UART_FCR(UART_BASE),(UART_FCR_Normal & ~UART_FCR_CLRT));
   else
      DRV_WriteReg(UART_FCR(UART_BASE),(UART_FCR_Normal & ~UART_FCR_CLRR));
}
void U_Close(UART_PORT port)
{
   kal_uint32 UART_BASE = UART_BaseAddr[port];
   
   UARTPort[port].initialized = KAL_FALSE;
   UARTPort[port].ownerid = MOD_UART1_HISR+port;

   switch(port)
   {
      case uart_port1:
         IRQMask(IRQ_UART1_CODE);
         break;
      case uart_port2:
         IRQMask(IRQ_UART2_CODE);
         break;
#ifdef __UART3_SUPPORT__
      case uart_port3:
         IRQMask(IRQ_UART3_CODE);
         break;
#endif   /*__UART3_SUPPORT__*/
      default:
         ASSERT(0);
         break;
   }
#ifdef __DMA_UART_VIRTUAL_FIFO__
   if(UART_VFIFO_support[port])
   {
		DMA_Stop(UARTPort[port].Rx_DMA_Ch);
		DMA_Stop(UARTPort[port].Tx_DMA_Ch);
   	DRV_WriteReg(UART_RXDMA(UART_BASE),UART_RXDMA_OFF);
   }	
#endif
   DRV_WriteReg(UART_IER(UART_BASE),UART_IER_ALLOFF);
   U_ConfigEscape(port, 0xff, 0);
   U_ClrRxBuffer(port);  /*clear sw RX buffer*/
   U_ClrTxBuffer(port);  /*clear sw TX buffer*/
   U_Purge(port, RX_BUF);/*clear sw RX FIFO*/