📄 gpio1.txt
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/****************************************************************************
*
* Name: gpio.c
*
* Copyright: (c) 2002 Conexant Systems Inc.
*
*****************************************************************************
****************************************************************************
* $Author: davidm $
* $Revision: 1.1 $
* $Modtime: 9/20/02 6:43p $
****************************************************************************/
/*
| Module Name: gpio.c
| Language: ARM C
|
| Description: This module is the General Purpose I/O (GPIO) functions.
|
| GPIO pins and register interface have two modes.
| The default mode consists of each set of 8 pins being
| controlled by an individual GP{X}_IO regiser.
|
| The GPIO register map are:
|
| GP0_IO = 0x00350010
| GP1_IO = 0x00350014
| GP2_IO = 0x00350018
| GP3_IO = 0x0035001C
|
| Bits Type Default Name Description
| [29:28] RW 0 GP3_ECM Event Counter Mode for Timer #4:
| 00 = normal GPIO[22]
| 01 = posedge event cntr for
| GPIO[22] input.
| 10 = negedge event cntr for
| GPIO[22] input.
| 11 = timer sq-wave output on
| GPIO[22].
| [27] RW 0 GP3_ISM GPIO interrupt sensitivity mode:
| 0 = active-lo level-sensitive.
| 1 = negative (hi-to-lo) edge-sensitive
| This control bit affects the mode
| for all GPIO[25:23] interrupt inputs.
| [26] RW 0 GP3_RFP A value of 1 enables GPIO[13:7]
| to be driven with internal RF
| power control signals from CUP.
| [25] RW 0 GP3_MODE A value of 0 enables the GPIO
| register interface in default
| mode where each set of 8 pins
| are controlled by a GP{x}_IO
| register. A value of 1 enables
| all 32 GPIO and/or GPOE bits to
| be read/write simultaneously.
| [24] RW 0 GP3_I2C A value of 1 enables GPIO[31:30]
| {SDA, SCL} to meet I2C transceiver
| electrical requirements.
| [23:16] Wd GP{X}_BWE If this field is equal to 0x00,
| then the whole GPIO byte register
| operates in normal RW mode. If any
| bit is set, then the corresponding
| GP_OE and GP_IO bit locations are
| enabled for writing. If the bit
| write enable is not set, the
| corresponding GPIO bits will be
| unaffected.
| [15:8] RW 0 GP{x}_OE A value of 1 enables corresponding
| GP_IO bit to be output on the GPIO
| pin.
| [7:0] RW 0 GP{x}_IO Writing provides data for GPIO
| output pin drivers. Reading accesses
| data directly from input pin buffers.
|
| GPIO = 0x00350010
|
| Bits Type Default Name Description
| [31:0] RW 0x00000000 GP_IO Writing provides data for GPIO output
| pin drivers. Reading accesses data
| directly from input pin buffers.
|
| GPOE = 0x00350014
|
| Bits Type Default Name Description
| [31:0] RW 0x00000000 GP_OE A value of 1 enables corresponding GP_IO
| bit to be output on the GPIO pin.
|
|
| Included Subprograms:
| GPIO_STATUS GPIO_Init(void)
| GPIO_STATUS GPIO_Config(GPIO_MODE eMode)
| GPIO_STATUS GPIO_32Bit_Write(UINT32 ulData, UINT32 ulOEnable)
| UINT32 GPIO_32Bit_Read(UINT32 ulDisableOE)
| GPIO_STATUS GPIO_8Bit_Write(volatile UINT32 *pulReg, UINT32 ulData, UINT8 ucOEnable)
| UINT8 GPIO_8Bit_Read(volatile UINT32 *pulReg, UINT8 ucDisableOE)
| GPIO_STATUS GPIO_Timer4_Event_Counter_Mode (TIMER4_EVENT_COUNTER_MODE eMode)
| GPIO_STATUS GPIO_Int_Sensitivity_Mode (GPIO_INT_SENSITIVITY_MODE eMode)
| GPIO_STATUS GPIO_RF_Power_Control (RF_POWER_CNTRL_MODE eMode)
| GPIO_STATUS GPIO_I2C_Mode (I2C_MODE eMode)
|
+==========================================================================+
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/arch/bspcfg.h>
#include <asm/arch/bsptypes.h>
#include <asm/arch/gpio.h>
#include <asm/arch/cnxtirq.h>
#include <asm/arch/cnxtbsp.h>
#include <asm/arch/syslib.h>
/* Exported Global Variable Declaration */
/* Local Global Variable Declaration */
/* Local Function Prototypes Declaration */
/*
+==========================================================================+
| CONEXANT SYSTEMS |
| PROPRIETARY AND CONFIDENTIAL |
| SUBPROGRAM HEADER |
+==========================================================================+
|
| Name: GPIO_Init
|
| Description: This routine initializes the GPIO registers.
|
| Parameters: None.
|
| Return: GPIO_STATUS - GPIO_STATUS_OK.
| GPIO_STATUS_ERROR.
|
+==========================================================================+
*/
GPIO_STATUS GPIO_Init(void)
{
signed int int_lvl;
static unsigned char GpioCallCnt = 0;
#ifdef DEVICE_YELLOWSTONE
*p_GRP3_INT_MASK = 0xFFFF0000;
*p_GRP3_OUTPUT_ENABLE = 0xFFFF0000;
*p_GRP3_INPUT_ENABLE = 0xFFFF0000;
*p_GRP3_DATA_OUT = 0xFFFF0000;
*p_GRP3_INT_EVENT_TYPE = 0xFFFF0000;
*p_GRP3_INT_ENABLE_POS = 0xFFFF0000;
*p_GRP3_INT_ENABLE_NEG = 0xFFFF0000;
*p_GRP3_INT_STAT_POS = 0xFFFF;
*p_GRP3_INT_STAT_NEG = 0xFFFF;
*p_GRP3_INT_STAT = 0xFFFF;
*p_GRP3_INT_ASSIGN_A = 0xFFFF0000;
*p_GRP3_INT_ASSIGN_B = 0xFFFF0000;
*p_GRP3_INT_ASSIGN_C = 0xFFFF0000;
*p_GRP3_INT_ASSIGN_D = 0xFFFF0000;
*p_GRP2_INT_MASK = 0xFFFF0000;
*p_GRP2_OUTPUT_ENABLE = 0xFFFF0000;
*p_GRP2_INPUT_ENABLE = 0xFFFF0000;
*p_GRP2_DATA_OUT = 0xFFFF0000;
*p_GRP2_INT_EVENT_TYPE = 0xFFFF0000;
*p_GRP2_INT_ENABLE_POS = 0xFFFF0000;
*p_GRP2_INT_ENABLE_NEG = 0xFFFF0000;
*p_GRP2_INT_STAT_POS = 0xFFFF;
*p_GRP2_INT_STAT_NEG = 0xFFFF;
*p_GRP2_INT_STAT = 0xFFFF;
*p_GRP2_INT_ASSIGN_A = 0xFFFF0000;
*p_GRP2_INT_ASSIGN_B = 0xFFFF0000;
*p_GRP2_INT_ASSIGN_C = 0xFFFF0000;
*p_GRP2_INT_ASSIGN_D = 0xFFFF0000;
*p_GRP1_INT_MASK = 0xFFFF0000;
*p_GRP1_OUTPUT_ENABLE = 0xFFFF0000;
*p_GRP1_INPUT_ENABLE = 0xFFFF0000;
*p_GRP1_DATA_OUT = 0xFFFF0000;
*p_GRP1_INT_EVENT_TYPE = 0xFFFF0000;
*p_GRP1_INT_ENABLE_POS = 0xFFFF0000;
*p_GRP1_INT_ENABLE_NEG = 0xFFFF0000;
*p_GRP1_INT_STAT_POS = 0xFFFF;
*p_GRP1_INT_STAT_NEG = 0xFFFF;
*p_GRP1_INT_STAT = 0xFFFF;
*p_GRP1_INT_ASSIGN_A = 0xFFFF0000;
*p_GRP1_INT_ASSIGN_B = 0xFFFF0000;
*p_GRP1_INT_ASSIGN_C = 0xFFFF0000;
*p_GRP1_INT_ASSIGN_D = 0xFFFF0000;
*p_GRP0_INT_MASK = 0xFFFF0000;
*p_GRP0_OUTPUT_ENABLE = 0xFFFF0000;
*p_GRP0_INPUT_ENABLE = 0xFFFF0000;
*p_GRP0_DATA_OUT = 0xFFFF0000;
*p_GRP0_INT_EVENT_TYPE = 0xFFFF0000;
*p_GRP0_INT_ENABLE_POS = 0xFFFF0000;
*p_GRP0_INT_ENABLE_NEG = 0xFFFF0000;
*p_GRP0_INT_STAT_POS = 0xFFFF;
*p_GRP0_INT_STAT_NEG = 0xFFFF;
*p_GRP0_INT_STAT = 0xFFFF;
*p_GRP0_INT_ASSIGN_A = 0xFFFF0000;
*p_GRP0_INT_ASSIGN_B = 0xFFFF0000;
*p_GRP0_INT_ASSIGN_C = 0xFFFF0000;
*p_GRP0_INT_ASSIGN_D = 0xFFFF0000;
#else
register UINT32 i = 0;
/* Should come from EEPROM in the future */
UINT32 uGPIODefaultValue[RUSHMORE_NUM_GPIODEFAULT] =
{
0x00000000, /*p_GRP0_ISM0: default to level IRQ*/
0x00000000, /*p_GRP0_ISM1: default to level IRQ*/
0x00000000, /*p_GRP0_ISM2: default to level IRQ*/
#if defined(CONFIG_CHIP_P52) || defined(CONFIG_CHIP_CX82110)
0x00000042, /* GPIO_OPT: Enable all chip selects except GPIO 33 for outer relay */
0x00003380, /* p_GRP0_OUTPUT_ENABLE */
0x000084bd, /* p_GRP1_OUTPUT_ENABLE */ /* 0x49C GPIO 21 output for inner relay */
0x0000007F, /* p_GRP2_OUTPUT_ENABLE */ /* GPIO38 output */
0xffff3040, /* p_GRP0_DATA_OUT */
0xffff049C, /* p_GRP1_DATA_OUT, 18, 19, and 20 LED OFF */
#endif
#ifdef CONFIG_CHIP_CX82100
0x000000c0, /*GPIO_OPT: Enable all chip selects */
0x000001e0, /*p_GRP0_OUTPUT_ENABLE */
0x0000011d, /*p_GRP1_OUTPUT_ENABLE */
0x00000000, /*p_GRP2_OUTPUT_ENABLE */
0xffff01e0, /*p_GRP0_DATA_OUT */
0xffff011c, /*p_GRP1_DATA_OUT */
#endif
0xffff003F, /*p_GRP2_DATA_OUT */
0xffffffff, /*p_GRP0_INT_STAT */
0xffffffff, /*p_GRP1_INT_STAT */
0xffffffff, /*p_GRP2_INT_STAT */
0xffff0000, /*p_GRP0_INT_MASK */
0xffff0000, /*p_GRP1_INT_MASK */
0xffff0000, /*p_GRP2_INT_MASK */
0xffff0000, /*GPIO_IPC1 */
0xffff0000, /*GPIO_IPC2 */
0xffff0000, /*GPIO_IPC3 */
/*RUSHMORE*/
0x00000000, /*p_GRP0_INPUT_ENABLE */
0x00000240, /*p_GRP1_INPUT_ENABLE */
0x00000080, /*p_GRP2_INPUT_ENABLE */
};
volatile UINT32 *pGPIODefaultReg[RUSHMORE_NUM_GPIODEFAULT] =
{
p_GRP0_ISM0,
p_GRP0_ISM1,
p_GRP0_ISM2,
GPIO_OPT,
p_GRP0_OUTPUT_ENABLE,
p_GRP1_OUTPUT_ENABLE,
p_GRP2_OUTPUT_ENABLE,
p_GRP0_DATA_OUT,
p_GRP1_DATA_OUT,
p_GRP2_DATA_OUT,
p_GRP0_INT_STAT,
p_GRP1_INT_STAT,
p_GRP2_INT_STAT,
p_GRP0_INT_MASK,
p_GRP1_INT_MASK,
p_GRP2_INT_MASK,
GPIO_IPC1,
GPIO_IPC2,
GPIO_IPC3,
/* RUSHMORE GPIO Registers. These are here even if device is not
Rushmore, but in that case, they are not initialized */
p_GRP0_INPUT_ENABLE,
p_GRP1_INPUT_ENABLE,
p_GRP2_INPUT_ENABLE,
};
GpioCallCnt++;
if (HWSTATE.eDeviceType >= DEVICE_RUSHMORE)
{
if( GpioCallCnt >=2 )
{
if( SYS_bDUALEMAC_Support() == TRUE )
{
int_lvl = intLock ();
*GPIO_OPT = 0x00000042;
*p_GRP0_DATA_OUT = 0xffff30E0;
HWSTATE.p_GRP0_INPUT_ENABLE_Image = *p_GRP0_OUTPUT_ENABLE = 0x000033E0;
( void ) intUnlock ( int_lvl );
}
}
else
{
for (i = 0; i < RUSHMORE_NUM_GPIODEFAULT; i++ )
{
*pGPIODefaultReg[i] = uGPIODefaultValue[i];
/* In Rushmore the 3 new GIO_IE register cannot be read. */
/* Thus we have keep an image of each to write to them */
/* without overwritten the previous value. */
switch ((UINT32) pGPIODefaultReg[i])
{
case (UINT32) p_GRP0_INPUT_ENABLE:
HWSTATE.p_GRP0_INPUT_ENABLE_Image = uGPIODefaultValue[i];
break;
case (UINT32) p_GRP1_INPUT_ENABLE:
HWSTATE.p_GRP1_INPUT_ENABLE_Image = uGPIODefaultValue[i];
break;
case (UINT32) p_GRP2_INPUT_ENABLE:
HWSTATE.p_GRP2_INPUT_ENABLE_Image = uGPIODefaultValue[i];
break;
default:
break;
}
}
}
}
else /* eDeviceType < RUSHMORE */
{
if( GpioCallCnt >=2 )
{
if( SYS_bDUALEMAC_Support() == TRUE )
{
int_lvl = intLock ();
*GPIO_OPT = 0x00000042 & ( ~0x2 );
*p_GRP0_DATA_OUT = 0xffff30E0;
*p_GRP0_OUTPUT_ENABLE = 0x000033E0;
( void ) intUnlock ( int_lvl );
}
}
else
{
for (i = 0; i < NUM_OF_GPIODEFAULT; i++)
{
if ( (UINT32 )GPIO_OPT == pGPIODefaultReg[i] && HWSTATE.eDeviceType != DEVICE_P5200X10)
*pGPIODefaultReg[i] = uGPIODefaultValue[i] & ( ~0x2 );
else
*pGPIODefaultReg[i] = uGPIODefaultValue[i];
}
}
}
#if defined(BOARD_BRONX_MACKINAC)
if( SYS_bADSL_Support() == FALSE )
{
/* Set GPIO31 as output port, OE2 */
*((UINT32*)0x3500b8) = *((UINT32*)0x3500b8) | 0x80008000;
/* Out 1 to GPIO31 to reset PCMCIA */
*((UINT32*)0x3500d0) = 0xffff841C;
for(i=0;i<0x30ffff;i++);
/* Out 0 to GPIO31 to release reset */
*((UINT32*)0x3500d0) = 0xffff041C;
for(i=0;i<0x30ffff;i++);
}
#endif /* End of BOARD_BRONX_MACKINAC */
#endif
return (GPIO_STATUS_OK);
}
/****************************************************************************
*
* Name: void SetGPIOUsage( UINT8 uGPIOPin, BOOL bOpt )
*
* Description: Sets the GPIO Usage via the option register
*
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