⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 fx2_full.lst

📁 USB开发的一些代码!适用于EX-USBFX2平台!这些源码还是蛮不错的!
💻 LST
📖 第 1 页 / 共 4 页
字号:
 510   2          case VX_B7: // read Speed
 511   2              {         
 512   3            EP0BUF[0] = VX_B7;
 513   3                SYNCDELAY;
 514   3                EP0BUF[1] = EZUSB_HIGHSPEED( );
 515   3                SYNCDELAY;
 516   3                EP0BUF[2] = enum_high_speed;
 517   3                SYNCDELAY;
 518   3                EP0BCH = 0;
 519   3                EP0BCL = 3;
 520   3                EP0CS |= bmHSNAK;
 521   3                break;
 522   3          }
 523   2          case VX_B8: // read EP6 State
 524   2              {         
 525   3            EP0BUF[0] = VX_B8;
 526   3                SYNCDELAY;
 527   3                EP0BUF[1] = EP6FIFOBCH;
 528   3                SYNCDELAY;
 529   3                EP0BUF[2] = EP6FIFOBCL;
 530   3                SYNCDELAY;
 531   3                EP0BUF[3] = EP6CS;
 532   3                SYNCDELAY;
 533   3                EP0BUF[4] = EP6FIFOFLGS;
 534   3                SYNCDELAY;
 535   3                EP0BUF[5] = EP6FIFOPFH;
 536   3                SYNCDELAY;
 537   3                EP0BUF[6] = EP6FIFOPFL;
 538   3                SYNCDELAY;
 539   3                EP0BCH = 0;
 540   3                EP0BCL = 7;
 541   3                EP0CS |= bmHSNAK;
 542   3                break;
 543   3          }
 544   2          case VX_B9: // read EP2 State
 545   2              {         
 546   3            EP0BUF[0] = VX_B9;
 547   3                SYNCDELAY;
 548   3                EP0BUF[1] = EP2FIFOBCH;
 549   3                SYNCDELAY;
 550   3                EP0BUF[2] = EP2FIFOBCL;
 551   3                SYNCDELAY;
C51 COMPILER V7.50   FX2_FULL                                                              07/21/2007 14:17:23 PAGE 10  

 552   3                EP0BUF[3] = EP2CS;
 553   3                SYNCDELAY;
 554   3                EP0BUF[4] = EP2FIFOFLGS;
 555   3                SYNCDELAY;
 556   3                EP0BUF[5] = EP2FIFOPFH;
 557   3                SYNCDELAY;
 558   3                EP0BUF[6] = EP2FIFOPFL;
 559   3                SYNCDELAY;
 560   3                EP0BCH = 0;
 561   3                EP0BCL = 7;
 562   3                EP0CS |= bmHSNAK;
 563   3                break;
 564   3          }
 565   2       
 566   2              case VX_BA:
 567   2                
 568   2                {
 569   3      
 570   3                {//IOC.2: LATCH, IOC.0: CLK, IOC.1: DATA, IOC.3: Reset
 571   4                int i;
 572   4                int d;
 573   4      
 574   4                d = SETUPDAT[2];
 575   4                d <<= 6;
 576   4              
 577   4                IOC |= 0xFC;
 578   4      
 579   4                
 580   4                for (i = 0; i < 8; i ++)
 581   4                      ;
 582   4                IOC &= 0xFB;  //set LATCH low
 583   4                for (i = 0; i < 10; i ++)
 584   4                      {
 585   5                      IOC &= 0xFE;  //set CLK low
 586   5              
 587   5                      if (d & 0x8000) //set DATA
 588   5                        IOC |= 0x2;
 589   5                      else
 590   5                        IOC &= 0xFD;
 591   5              
 592   5                      IOC &= 0xFE;  //set CLK low
 593   5                      IOC &= 0xFE;  //set CLK low
 594   5                      IOC &= 0xFE;  //set CLK low
 595   5                      IOC |= 0x1;   //set CLK high
 596   5                      IOC |= 0x1;   //set CLK high
 597   5                      IOC |= 0x1;   //set CLK high
 598   5              
 599   5                      d <<= 1;
 600   5                      }
 601   4      
 602   4                IOC |= 0xFC;  //set LATCH high
 603   4                }
 604   3              
 605   3                EP0BUF[0] = VX_BA;
 606   3                SYNCDELAY;
 607   3                EP0BUF[1] = SETUPDAT[2];
 608   3                SYNCDELAY;
 609   3                EP0BCH = 0;
 610   3                EP0BCL = 2;
 611   3                EP0CS |= bmHSNAK;
 612   3                break;
 613   3                }
C51 COMPILER V7.50   FX2_FULL                                                              07/21/2007 14:17:23 PAGE 11  

 614   2      
 615   2      
 616   2              case VX_BB:
 617   2                {
 618   3                {//IOC.2: LATCH, IOC.0: CLK, IOC.1: DATA, IOC.4: Reset
 619   4                int i;
 620   4                int d;
 621   4      
 622   4                d = 0x100 | SETUPDAT[2];
 623   4                d <<= 6;
 624   4              
 625   4                IOC |= 0xFC;
 626   4                for (i = 0; i < 8; i ++)
 627   4                      ;
 628   4                IOC &= 0xFB;  //set LATCH low
 629   4                for (i = 0; i < 10; i ++)
 630   4                      {
 631   5                      IOC &= 0xFE;  //set CLK low
 632   5              
 633   5                      if (d & 0x8000) //set DATA
 634   5                        IOC |= 0x2;
 635   5                      else
 636   5                        IOC &= 0xFD;
 637   5              
 638   5                      IOC &= 0xFE;  //set CLK low
 639   5                      IOC &= 0xFE;  //set CLK low
 640   5                      IOC &= 0xFE;  //set CLK low
 641   5                      IOC |= 0x1;   //set CLK high
 642   5                      IOC |= 0x1;   //set CLK high
 643   5                      IOC |= 0x1;   //set CLK high
 644   5              
 645   5                      d <<= 1;
 646   5                      }
 647   4                IOC |= 0xFC;  //set LATCH high
 648   4                }
 649   3              
 650   3                EP0BUF[0] = VX_BB;
 651   3                SYNCDELAY;
 652   3                EP0BUF[1] = SETUPDAT[2];
 653   3                SYNCDELAY;
 654   3                EP0BCH = 0;
 655   3                EP0BCL = 2;
 656   3                EP0CS |= bmHSNAK;
 657   3                break;
 658   3                }
 659   2                
 660   2                
 661   2                //liuyunxiang
 662   2                case VX_BE_CONF_START:
 663   2                      {
 664   3                              conf_start = TRUE;
 665   3                              xfer_times = (SETUPDAT[2] << 8) + SETUPDAT[3];
 666   3                              //xfer_times = 488;
 667   3                              times_xfered = 0;
 668   3                              
 669   3                      EP2FIFOCFG &= 0xE7;             //configure ep2fifo as manual mode                   
 670   3                        SYNCDELAY;                    
 671   3                              
 672   3                              *EP0BUF = CONF_START_SUCCESS;
 673   3                      EP0BCH = 0;
 674   3                      EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
 675   3                      EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
C51 COMPILER V7.50   FX2_FULL                                                              07/21/2007 14:17:23 PAGE 12  

 676   3                              break;
 677   3                      }
 678   2      
 679   2      /*
 680   2            {
 681   2                      OEC |= 0x0F;  //Enable the PC0/PC1(PC0:CLK   PC1:SDI)
 682   2                      OEA &= 0xFB;  //Enable the PA2
 683   2      //              IOA &= 0x00;  //
 684   2              
 685   2                      ///Followed codes testing the RESET function
 686   2      //              IOC |= 0xF7;  // Enable reset
 687   2      //              EZUSB_Delay(1);
 688   2      //              IOC |= 0x08;  // Return reset to high
 689   2                      ///The codes above testing the RESET function
 690   2      
 691   2                      ///Followed codes testing the variable digital potentiometer
 692   2                      IOC &= 0xFB;  //Enable CS(LOW, PC2) 0xFB=0x11111011
 693   2      
 694   2              IOC &= 0xFC;  //Clean
 695   2                      IOC &= 0xFC;  //Set SDI A1=0 (Enable channel 2)(0x1111 1100)
 696   2                      IOC |= 0x01;  //CLK
 697   2                      IOC |= 0x01;
 698   2                      IOC &= 0xFC;  //Clean
 699   2      
 700   2                      IOC |= 0x02;  //Set SDI A0=1 (Enable channel 2)
 701   2                      IOC |= 0x01;  //CLK
 702   2                      IOC |= 0x01;
 703   2                      IOC &= 0xFC;  //Clean
 704   2      
 705   2                      IOC &= 0xFC;  //Set SDI D7=0
 706   2                      IOC |= 0x01;  //CLK
 707   2                      IOC |= 0x01;
 708   2                      IOC &= 0xFC;  //Clean
 709   2      
 710   2                      IOC |= 0x02;  //Set SDI D6=1
 711   2                      IOC |= 0x01;  //CLK
 712   2                      IOC |= 0x01;
 713   2                      IOC &= 0xFC;  //Clean
 714   2      
 715   2                      IOC &= 0xFC;  //Set SDI D5=0
 716   2                      IOC |= 0x01;  //CLK
 717   2                      IOC |= 0x01;
 718   2                      IOC &= 0xFC;  //Clean
 719   2      
 720   2                      IOC &= 0xFC;  //Set SDI D4=0
 721   2                      IOC |= 0x01;  //CLK
 722   2                      IOC |= 0x01;
 723   2                      IOC &= 0xFC;  //Clean
 724   2      
 725   2                      IOC &= 0xFC;  //Set SDI D3=0
 726   2                      IOC |= 0x01;  //CLK
 727   2                      IOC |= 0x01;
 728   2                      IOC &= 0xFC;  //Clean
 729   2      
 730   2                      IOC &= 0xFC;  //Set SDI D2=0
 731   2                      IOC |= 0x01;  //CLK
 732   2                      IOC |= 0x01;
 733   2                      IOC &= 0xFC;  //Clean
 734   2      
 735   2                      IOC &= 0xFC;  //Set SDI D1=0
 736   2                      IOC |= 0x01;  //CLK
 737   2                      IOC |= 0x01;
C51 COMPILER V7.50   FX2_FULL                                                              07/21/2007 14:17:23 PAGE 13  

 738   2                      IOC &= 0xFC;  //Clean
 739   2      
 740   2                      IOC &= 0xFC;  //Set SDI D0=0
 741   2                      IOC |= 0x01;  //CLK
 742   2                      IOC |= 0x01;
 743   2                      IOC &= 0xFC;  //Clean 
 744   2      
 745   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 746   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 747   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 748   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 749   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 750   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 751   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 752   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 753   2                      IOC |= 0x04;  //Return CS to High (to store the value in VR)
 754   2      
 755   2      
 756   2      
 757   2      
 758   2      
 759   2      
 760   2      
 761   2      
 762   2      
 763   2      
 764   2      
 765   2      
 766   2      
 767   2                      IOC &= 0xFB;  //Enable CS(LOW, PC2) 0xFB=0x11111011
 768   2                      IOC &= 0xFB;  //Enable CS(LOW, PC2) 0xFB=0x11111011

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -