📄 fx2_full.lst
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251 3
252 3 if(times_xfered == xfer_times)
253 3 { //finalize transfering the configuration file
254 4 conf_start = FALSE;
255 4 //if(IOE &= 0x10) //if CONF_DONE == 1
256 4 // { //fpga configuration success
257 4 for(i = 0; i < 10; i++)
258 4 {
259 5 IOE &= 0xFD; //DCLK = 0;
260 5 IOE |= 0x02; //DCLK = 1;
261 5 }
262 4 EP2FIFOCFG |= 0x18; //configure ep2fifo as auto mode
263 4 }
264 3 SYNCDELAY;
265 3 EP2BCL = 0x80; // re(arm) EP2OUT
266 3 }
267 2 }
268 1 else
269 1 {
270 2 if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
271 2 {
272 3 //if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
273 3 if ( EP24FIFOFLGS & 0x04 ) // if there's more than 512 bytes in EP2 FIFO
274 3 {
275 4 if ( EXTFIFONOTFULL ) // if the external FIFO is not full
276 4 {
277 5 if(enum_high_speed)
278 5 {
279 6 SYNCDELAY;
280 6 GPIFTCB1 = 0x00; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
281 6 SYNCDELAY;
282 6 GPIFTCB0 = 0xFF;
283 6 SYNCDELAY;
284 6 }
285 5 else
286 5 {
287 6 SYNCDELAY;
288 6 GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
289 6 SYNCDELAY;
290 6 GPIFTCB0 = 0x1F;
291 6 SYNCDELAY;
292 6 }
293 5
294 5 GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
295 5 SYNCDELAY;
296 5
297 5 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
298 5 {
299 6 ;
300 6 }
301 5 SYNCDELAY;
302 5 }
303 4 }
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 6
304 3 }
305 2
306 2 if(in_enable) // if IN transfers are enabled
307 2 {
308 3 if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
309 3 {
310 4 if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
311 4 {
312 5 //if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
313 5 if ( ( EP68FIFOFLGS & 0x04 ) ) // if EP6 FIFO is less than 1023
314 5 {
315 6 if(enum_high_speed)
316 6 {
317 7 SYNCDELAY;
318 7 GPIFTCB1 = 0x00; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
319 7 SYNCDELAY;
320 7 GPIFTCB0 = 0xFF;
321 7 SYNCDELAY;
322 7 }
323 6
324 6 else
325 6 {
326 7 SYNCDELAY;
327 7 GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
328 7 SYNCDELAY;
329 7 GPIFTCB0 = 0x1F;
330 7 SYNCDELAY;
331 7 }
332 6
333 6 GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
334 6 SYNCDELAY;
335 6
336 6 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
337 6 {
338 7 ;
339 7 }
340 6
341 6 SYNCDELAY;
342 6 }
343 5 }
344 4 }
345 3 }
346 2 }
347 1 }
348
349 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
350 {
351 1 return(TRUE);
352 1 }
353
354 BOOL TD_Resume(void) // Called after the device resumes
355 {
356 1 return(TRUE);
357 1 }
358
359 //-----------------------------------------------------------------------------
360 // Device Request hooks
361 // The following hooks are called by the end point 0 device request parser.
362 //-----------------------------------------------------------------------------
363
364 BOOL DR_GetDescriptor(void)
365 {
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 7
366 1 return(TRUE);
367 1 }
368
369 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
370 {
371 1 if( EZUSB_HIGHSPEED( ) )
372 1 { // FX2 enumerated at high speed
373 2 SYNCDELAY; //
374 2 EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
375 2 SYNCDELAY; //
376 2 EP6AUTOINLENL = 0x00;
377 2 SYNCDELAY;
378 2 enum_high_speed = TRUE;
379 2 }
380 1 else
381 1 { // FX2 enumerated at full speed
382 2 SYNCDELAY;
383 2 EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
384 2 SYNCDELAY;
385 2 EP6AUTOINLENL = 0x40;
386 2 SYNCDELAY;
387 2 enum_high_speed = FALSE;
388 2 }
389 1
390 1 Configuration = SETUPDAT[2];
391 1 return(TRUE); // Handled by user code
392 1 }
393
394 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
395 {
396 1 EP0BUF[0] = Configuration;
397 1 EP0BCH = 0;
398 1 EP0BCL = 1;
399 1 return(TRUE); // Handled by user code
400 1 }
401
402 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
403 {
404 1 AlternateSetting = SETUPDAT[2];
405 1 return(TRUE); // Handled by user code
406 1 }
407
408 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
409 {
410 1 EP0BUF[0] = AlternateSetting;
411 1 EP0BCH = 0;
412 1 EP0BCL = 1;
413 1 return(TRUE); // Handled by user code
414 1 }
415
416 BOOL DR_GetStatus(void)
417 {
418 1 return(TRUE);
419 1 }
420
421 BOOL DR_ClearFeature(void)
422 {
423 1 return(TRUE);
424 1 }
425
426 BOOL DR_SetFeature(void)
427 {
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 8
428 1 return(TRUE);
429 1 }
430
431 #define VX_B2 0xB2 // reset the external FIFO
432 #define VX_B3 0xB3 // enable IN transfers
433 #define VX_B4 0xB4 // disable IN transfers
434 #define VX_B5 0xB5 // read GPIFREADYSTAT register
435 #define VX_B6 0xB6 // read GPIFTRIG register
436 #define VX_B7 0xB7 // read Highspeed/Fullspeed
437 #define VX_B8 0xB8 // read EP6 States
438 #define VX_B9 0xB9 // read EP2 States
439 #define VX_BA 0xBA // set digital potentiometers channel 1
440 #define VX_BB 0xBB // set digital potentiometers channel 2
441
442 //liuyunxiang
443 //#define VX_BE_CONF_INIT 0xBE //initialize fpga configuration
444 #define VX_BE_CONF_START 0xBE //start fpga configuration
445 #define CONF_START_FAIL 0x00 //start fpga configuration error
446 #define CONF_START_SUCCESS 0x01 //start fpga configuration success
447
448
449 BOOL DR_VendorCmnd(void)
450 {
451 1 switch (SETUPDAT[1])
452 1 {
453 2 case VX_B2:
454 2 {
455 3 // reset the external FIFO
456 3
457 3 OEA |= 0x10; // turn on PA4 as output pin (PA4 as aclr of FPGA FIFO)
458 3 IOA |= 0x10; // pull PA4 high initially
459 3 IOA &= 0xEF; // bring PA4 low
460 3 EZUSB_Delay (1); // keep PA4 low for ~1ms, more than enough time
461 3 IOA |= 0x10; // bring PA4 high
462 3
463 3 *EP0BUF = VX_B2;
464 3 EP0BCH = 0;
465 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
466 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
467 3 break;
468 3 }
469 2 case VX_B3: // enable IN transfers
470 2 {
471 3 in_enable = TRUE;
472 3 *EP0BUF = VX_B3;
473 3 EP0BCH = 0;
474 3 EP0BCL = 1;
475 3 EP0CS |= bmHSNAK;
476 3 break;
477 3 }
478 2 case VX_B4: // disable IN transfers
479 2 {
480 3 in_enable = FALSE;
481 3
482 3 *EP0BUF = VX_B4;
483 3 EP0BCH = 0;
484 3 EP0BCL = 1;
485 3 EP0CS |= bmHSNAK;
486 3 break;
487 3 }
488 2 case VX_B5: // read GPIFREADYSTAT register
489 2 {
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 9
490 3 EP0BUF[0] = VX_B5;
491 3 SYNCDELAY;
492 3 EP0BUF[1] = GPIFREADYSTAT;
493 3 SYNCDELAY;
494 3 EP0BCH = 0;
495 3 EP0BCL = 2;
496 3 EP0CS |= bmHSNAK;
497 3 break;
498 3 }
499 2 case VX_B6: // read GPIFTRIG register
500 2 {
501 3 EP0BUF[0] = VX_B6;
502 3 SYNCDELAY;
503 3 EP0BUF[1] = GPIFTRIG;
504 3 SYNCDELAY;
505 3 EP0BCH = 0;
506 3 EP0BCL = 2;
507 3 EP0CS |= bmHSNAK;
508 3 break;
509 3 }
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