📄 fx2_full.lst
字号:
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE FX2_FULL
OBJECT MODULE PLACED IN FX2_full.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE FX2_full.c DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: FX2_full.c
4 // Contents: Hooks required to implement FX2 GPIF to external FPGA
5 // interface
6 //-----------------------------------------------------------------------------
7 #include "fx2.h"
8 #include "fx2regs.h"
9 #include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
10 // Ref. Manual for usage details.
11
12 #define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
13 #define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
14
15 #define GPIFTRIGRD 4
16
17 #define GPIF_EP2 0
18 #define GPIF_EP4 1
19 #define GPIF_EP6 2
20 #define GPIF_EP8 3
21
22 extern BOOL GotSUD; // Received setup data flag
23 extern BOOL Sleep;
24 extern BOOL Rwuen;
25 extern BOOL Selfpwr;
26
27 BYTE Configuration; // Current configuration
28 BYTE AlternateSetting; // Alternate settings
29 BOOL in_enable = FALSE; // flag to enable IN transfers
30 BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
31
32
33 //liuyunxiang
34 WORD count = 0;
35 BOOL conf_start = FALSE;
36 WORD xfer_times = 0; //the total times of transfering the configuration file
37 WORD times_xfered = 0;
38 //WORD port_e_status = 0;
39
40
41
42 //-----------------------------------------------------------------------------
43 // Task Dispatcher hooks
44 // The following hooks are called by the task dispatcher.
45 //-----------------------------------------------------------------------------
46 void GpifInit ();
47
48 void TD_Init(void) // Called once at startup
49 {
50 1 // set the CPU clock to 48MHz
51 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
52 1 SYNCDELAY;
53 1
54 1 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
55 1 SYNCDELAY;
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 2
56 1 EP4CFG = 0x00; // EP4 not valid
57 1 SYNCDELAY;
58 1 EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
59 1 SYNCDELAY;
60 1 EP8CFG = 0x00; // EP8 not valid
61 1 SYNCDELAY;
62 1
63 1
64 1 FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
65 1 SYNCDELAY;
66 1 FIFORESET = 0x02; // reset EP2 FIFO
67 1 SYNCDELAY;
68 1 FIFORESET = 0x06; // reset EP6 FIFO
69 1 SYNCDELAY;
70 1 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
71 1 SYNCDELAY;
72 1
73 1 EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
74 1 SYNCDELAY;
75 1 EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
76 1 SYNCDELAY;
77 1 EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
78 1 SYNCDELAY;
79 1
80 1 EP6FIFOPFH = 0x18; // no more than 3 512-byte packets in EP6 FIFO
81 1 SYNCDELAY;
82 1 EP6FIFOPFL = 0x00;
83 1 SYNCDELAY;
84 1
85 1 /*
86 1 EP2FIFOPFH = 0x82; // more than 512 bytes in EP2 FIFO //seemed to be wrong
87 1 SYNCDELAY;
88 1 EP2FIFOPFL = 0x00;
89 1 SYNCDELAY;
90 1 */
91 1
92 1 if( EZUSB_HIGHSPEED( ) )
93 1 { // FX2 enumerated at high speed
94 2 SYNCDELAY; //
95 2 EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
96 2 SYNCDELAY; //
97 2 EP6AUTOINLENL = 0x00;
98 2 SYNCDELAY;
99 2 enum_high_speed = TRUE;
100 2 }
101 1 else
102 1 { // FX2 enumerated at full speed
103 2 SYNCDELAY;
104 2 EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
105 2 SYNCDELAY;
106 2 EP6AUTOINLENL = 0x40;
107 2 SYNCDELAY;
108 2 enum_high_speed = FALSE;
109 2 }
110 1
111 1
112 1 GpifInit (); // initialize GPIF registers
113 1
114 1 SYNCDELAY;
115 1 EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
116 1 SYNCDELAY;
117 1 EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 3
118 1 SYNCDELAY;
119 1
120 1 // reset the external FIFO
121 1
122 1 OEA |= 0x10; // turn on PA4 as output pin (PA4 as aclr of FPGA FIFO)
123 1 IOA |= 0x10; // pull PA4 high initially
124 1 IOA &= 0xEF; // bring PA4 low
125 1 EZUSB_Delay (1); // keep PA4 low for ~1ms, more than enough time
126 1 IOA |= 0x10; // bring PA4 high
127 1
128 1 SYNCDELAY;
129 1
130 1
131 1 // Configure GPIF Address pins to be normal port pins
132 1 PORTCCFG = 0x00;
133 1 OEC = 0xFF; // as outputs
134 1 PORTECFG |= 0x00;
135 1 OEE |= 0xFF; // as outputs
136 1
137 1 IOC = 0xFF;
138 1
139 1 //liuyunxiang
140 1 count = 0;
141 1 PORTECFG = 0x00;
142 1 OEE |= 0xFF; // as outputs
143 1 IFCONFIG &= 0xFB; // set GSTATE bit to 0, configure PE.2:0 as general i/o pins
144 1
145 1 //liuyunxiang
146 1 AUTOPTRSETUP |= 0x01; // enable dual autopointer feature
147 1
148 1 //liuyunxiang
149 1 //pe0 DATA0 out
150 1 //pe1 DCLK out
151 1 //pe2 nCONFIG out
152 1 //pe3 nSTATUS in
153 1 //pe4 CONF_DONE in
154 1
155 1 //liuyunxiang
156 1 OEE |= 0x01; // turn on PE0 as output pin
157 1 SYNCDELAY;
158 1 OEE |= 0x02; // turn on PE1 as output pin
159 1 SYNCDELAY;
160 1 OEE |= 0x04; // turn on PE2 as output pin
161 1 SYNCDELAY;
162 1 OEE &= 0xF7; // turn on PE3 as intput pin
163 1 SYNCDELAY;
164 1 OEE &= 0xEF; // turn on PE4 as intput pin
165 1 SYNCDELAY;
166 1
167 1 //liuyunxiang
168 1 IOE |= 0x04; // nCONFIG = 1;
169 1 SYNCDELAY;
170 1 IOE &= 0xFD; // DCLK = 0;
171 1 SYNCDELAY;
172 1
173 1 }
174
175 void TD_Poll(void)
176 {
177 1 //liuyunxiang
178 1 WORD i,j;
179 1 BYTE tempbuffer;
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 4
180 1
181 1 //liuyunxiang
182 1 if(conf_start)
183 1 { //start xfering configuration file
184 2 if(times_xfered == 0)
185 2 { //initial xfering configuration file
186 3 SYNCDELAY;
187 3 IOE &= 0xFD; // DCLK = 0;
188 3 SYNCDELAY;
189 3
190 3 IOE &= 0xFB; //nCONFIG = 0; //turn nCONFIG low
191 3 //EZUSB_Delay(10000);
192 3 SYNCDELAY;
193 3
194 3 EZUSB_Delay(1);
195 3
196 3 // if((IOE &= 0x08) == 0)
197 3
198 3 // SYNCDELAY;
199 3 // {
200 3 IOE |= 0x04; //nCONFIG = 1;
201 3 SYNCDELAY;
202 3 // }
203 3 // else
204 3 // {
205 3 // conf_start = FALSE;
206 3 // return;
207 3 // }
208 3 }
209 2 if(!(EP2468STAT & bmEP2EMPTY))
210 2 { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
211 3
212 3 // Source is EP2OUT
213 3 APTR1H = MSB( &EP2FIFOBUF );
214 3 APTR1L = LSB( &EP2FIFOBUF );
215 3
216 3 count = (EP2BCH << 8) + EP2BCL;
217 3
218 3 for( i = 0x0000; i < count; i++ )
219 3 {
220 4 tempbuffer = EXTAUTODAT1;
221 4
222 4 //test
223 4 //EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[tempbuffer >> 4]));
224 4 //EZUSB_Delay(50);
225 4 //EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[tempbuffer & 0x0F]));
226 4 //EZUSB_Delay(50);
227 4
228 4 for(j = 0; j < 8; j++)
229 4 {
230 5 IOE &= 0xFD; //DCLK = 0;
231 5
232 5 if((tempbuffer & 0x01) == 1)
233 5 {
234 6 IOE |= 0x01; //set 1 to DATA0
235 6 }
236 5 else
237 5 {
238 6 IOE &= 0xFE; //set 0 to DATA0
239 6 }
240 5 IOE |= 0x02; //DCLK = 1;
241 5 // if(!(IOE &= 0x08)) //if nSTATUS == 0
C51 COMPILER V7.50 FX2_FULL 07/21/2007 14:17:23 PAGE 5
242 5 // {
243 5 // //nSTATUS == 0; error, should retransfer...
244 5 // }
245 5 tempbuffer >>= 1;
246 5 }
247 4 }
248 3
249 3 times_xfered++;
250 3 SYNCDELAY;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -