📄 fx2_full.c
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#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: FX2_full.c
// Contents: Hooks required to implement FX2 GPIF to external FPGA
// interface
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
// Ref. Manual for usage details.
#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
#define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
BOOL in_enable = FALSE; // flag to enable IN transfers
BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
//liuyunxiang
WORD count = 0;
BOOL conf_start = FALSE;
WORD xfer_times = 0; //the total times of transfering the configuration file
WORD times_xfered = 0;
//WORD port_e_status = 0;
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void GpifInit ();
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
SYNCDELAY;
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
SYNCDELAY;
EP4CFG = 0x00; // EP4 not valid
SYNCDELAY;
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 not valid
SYNCDELAY;
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOPFH = 0x18; // no more than 3 512-byte packets in EP6 FIFO
SYNCDELAY;
EP6FIFOPFL = 0x00;
SYNCDELAY;
/*
EP2FIFOPFH = 0x82; // more than 512 bytes in EP2 FIFO //seemed to be wrong
SYNCDELAY;
EP2FIFOPFL = 0x00;
SYNCDELAY;
*/
if( EZUSB_HIGHSPEED( ) )
{ // FX2 enumerated at high speed
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
GpifInit (); // initialize GPIF registers
SYNCDELAY;
EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
SYNCDELAY;
EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
SYNCDELAY;
// reset the external FIFO
OEA |= 0x10; // turn on PA4 as output pin (PA4 as aclr of FPGA FIFO)
IOA |= 0x10; // pull PA4 high initially
IOA &= 0xEF; // bring PA4 low
EZUSB_Delay (1); // keep PA4 low for ~1ms, more than enough time
IOA |= 0x10; // bring PA4 high
SYNCDELAY;
// Configure GPIF Address pins to be normal port pins
PORTCCFG = 0x00;
OEC = 0xFF; // as outputs
PORTECFG |= 0x00;
OEE |= 0xFF; // as outputs
IOC = 0xFF;
//liuyunxiang
count = 0;
PORTECFG = 0x00;
OEE |= 0xFF; // as outputs
IFCONFIG &= 0xFB; // set GSTATE bit to 0, configure PE.2:0 as general i/o pins
//liuyunxiang
AUTOPTRSETUP |= 0x01; // enable dual autopointer feature
//liuyunxiang
//pe0 DATA0 out
//pe1 DCLK out
//pe2 nCONFIG out
//pe3 nSTATUS in
//pe4 CONF_DONE in
//liuyunxiang
OEE |= 0x01; // turn on PE0 as output pin
SYNCDELAY;
OEE |= 0x02; // turn on PE1 as output pin
SYNCDELAY;
OEE |= 0x04; // turn on PE2 as output pin
SYNCDELAY;
OEE &= 0xF7; // turn on PE3 as intput pin
SYNCDELAY;
OEE &= 0xEF; // turn on PE4 as intput pin
SYNCDELAY;
//liuyunxiang
IOE |= 0x04; // nCONFIG = 1;
SYNCDELAY;
IOE &= 0xFD; // DCLK = 0;
SYNCDELAY;
}
void TD_Poll(void)
{
//liuyunxiang
WORD i,j;
BYTE tempbuffer;
//liuyunxiang
if(conf_start)
{ //start xfering configuration file
if(times_xfered == 0)
{ //initial xfering configuration file
SYNCDELAY;
IOE &= 0xFD; // DCLK = 0;
SYNCDELAY;
IOE &= 0xFB; //nCONFIG = 0; //turn nCONFIG low
//EZUSB_Delay(10000);
SYNCDELAY;
EZUSB_Delay(1);
// if((IOE &= 0x08) == 0)
// SYNCDELAY;
// {
IOE |= 0x04; //nCONFIG = 1;
SYNCDELAY;
// }
// else
// {
// conf_start = FALSE;
// return;
// }
}
if(!(EP2468STAT & bmEP2EMPTY))
{ // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
// Source is EP2OUT
APTR1H = MSB( &EP2FIFOBUF );
APTR1L = LSB( &EP2FIFOBUF );
count = (EP2BCH << 8) + EP2BCL;
for( i = 0x0000; i < count; i++ )
{
tempbuffer = EXTAUTODAT1;
//test
//EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[tempbuffer >> 4]));
//EZUSB_Delay(50);
//EZUSB_WriteI2C(LED_ADDR, 0x01, &(Digit[tempbuffer & 0x0F]));
//EZUSB_Delay(50);
for(j = 0; j < 8; j++)
{
IOE &= 0xFD; //DCLK = 0;
if((tempbuffer & 0x01) == 1)
{
IOE |= 0x01; //set 1 to DATA0
}
else
{
IOE &= 0xFE; //set 0 to DATA0
}
IOE |= 0x02; //DCLK = 1;
// if(!(IOE &= 0x08)) //if nSTATUS == 0
// {
// //nSTATUS == 0; error, should retransfer...
// }
tempbuffer >>= 1;
}
}
times_xfered++;
SYNCDELAY;
if(times_xfered == xfer_times)
{ //finalize transfering the configuration file
conf_start = FALSE;
//if(IOE &= 0x10) //if CONF_DONE == 1
// { //fpga configuration success
for(i = 0; i < 10; i++)
{
IOE &= 0xFD; //DCLK = 0;
IOE |= 0x02; //DCLK = 1;
}
EP2FIFOCFG |= 0x18; //configure ep2fifo as auto mode
}
SYNCDELAY;
EP2BCL = 0x80; // re(arm) EP2OUT
}
}
else
{
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
//if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
if ( EP24FIFOFLGS & 0x04 ) // if there's more than 512 bytes in EP2 FIFO
{
if ( EXTFIFONOTFULL ) // if the external FIFO is not full
{
if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0xFF;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x1F;
SYNCDELAY;
}
GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
SYNCDELAY;
}
}
}
if(in_enable) // if IN transfers are enabled
{
if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
{
//if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
if ( ( EP68FIFOFLGS & 0x04 ) ) // if EP6 FIFO is less than 1023
{
if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0xFF;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x1F;
SYNCDELAY;
}
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
SYNCDELAY;
}
}
}
}
}
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
if( EZUSB_HIGHSPEED( ) )
{ // FX2 enumerated at high speed
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
#define VX_B2 0xB2 // reset the external FIFO
#define VX_B3 0xB3 // enable IN transfers
#define VX_B4 0xB4 // disable IN transfers
#define VX_B5 0xB5 // read GPIFREADYSTAT register
#define VX_B6 0xB6 // read GPIFTRIG register
#define VX_B7 0xB7 // read Highspeed/Fullspeed
#define VX_B8 0xB8 // read EP6 States
#define VX_B9 0xB9 // read EP2 States
#define VX_BA 0xBA // set digital potentiometers channel 1
#define VX_BB 0xBB // set digital potentiometers channel 2
//liuyunxiang
//#define VX_BE_CONF_INIT 0xBE //initialize fpga configuration
#define VX_BE_CONF_START 0xBE //start fpga configuration
#define CONF_START_FAIL 0x00 //start fpga configuration error
#define CONF_START_SUCCESS 0x01 //start fpga configuration success
BOOL DR_VendorCmnd(void)
{
switch (SETUPDAT[1])
{
case VX_B2:
{
// reset the external FIFO
OEA |= 0x10; // turn on PA4 as output pin (PA4 as aclr of FPGA FIFO)
IOA |= 0x10; // pull PA4 high initially
IOA &= 0xEF; // bring PA4 low
EZUSB_Delay (1); // keep PA4 low for ~1ms, more than enough time
IOA |= 0x10; // bring PA4 high
*EP0BUF = VX_B2;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_B3: // enable IN transfers
{
in_enable = TRUE;
*EP0BUF = VX_B3;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
}
case VX_B4: // disable IN transfers
{
in_enable = FALSE;
*EP0BUF = VX_B4;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
}
case VX_B5: // read GPIFREADYSTAT register
{
EP0BUF[0] = VX_B5;
SYNCDELAY;
EP0BUF[1] = GPIFREADYSTAT;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
break;
}
case VX_B6: // read GPIFTRIG register
{
EP0BUF[0] = VX_B6;
SYNCDELAY;
EP0BUF[1] = GPIFTRIG;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
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