📄 post.h
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}
__inline VOID DM_Error(PCHAR fmt, ...)
{
CHAR pstring[100];
va_list ap;
PVOID p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12;
sprintf(pstring, "\n");
PrintLcd(pstring);
if (PrintFlag)
{
PrintSerial(pstring, SerialPort);
}
va_start(ap, fmt);
p1 = va_arg(ap, PVOID);
p2 = va_arg(ap, PVOID);
p3 = va_arg(ap, PVOID);
p4 = va_arg(ap, PVOID);
p5 = va_arg(ap, PVOID);
p6 = va_arg(ap, PVOID);
p7 = va_arg(ap, PVOID);
p8 = va_arg(ap, PVOID);
p9 = va_arg(ap, PVOID);
p10 = va_arg(ap, PVOID);
p11 = va_arg(ap, PVOID);
p12 = va_arg(ap, PVOID);
va_end(ap);
sprintf(pstring, fmt, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12);
PrintLcd(pstring);
if (PrintFlag)
{
PrintSerial(pstring, SerialPort);
}
sprintf(pstring, "\n");
PrintLcd(pstring);
if (PrintFlag)
{
PrintSerial(pstring, SerialPort);
}
}
__inline VOID DM_CwDbgPrintf(UINT contrlWord, PCHAR fmt, ...)
{
CHAR pstring[100];
va_list ap;
PVOID p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12;
if (contrlWord && PrintFlag)
{
sprintf(pstring, "\n");
PrintSerial(pstring, SerialPort);
va_start(ap, fmt);
p1 = va_arg(ap, PVOID);
p2 = va_arg(ap, PVOID);
p3 = va_arg(ap, PVOID);
p4 = va_arg(ap, PVOID);
p5 = va_arg(ap, PVOID);
p6 = va_arg(ap, PVOID);
p7 = va_arg(ap, PVOID);
p8 = va_arg(ap, PVOID);
p9 = va_arg(ap, PVOID);
p10 = va_arg(ap, PVOID);
p11 = va_arg(ap, PVOID);
p12 = va_arg(ap, PVOID);
va_end(ap);
sprintf(pstring, fmt, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12);
PrintSerial(pstring, SerialPort);
sprintf(pstring, "\n");
PrintSerial(pstring, SerialPort);
}
}
__inline VOID DM_ControlWordsDebugPrintPutBit(UINT controlWord, INT flag)
{
}
__inline VOID DM_StartTest(PCHAR test)
{
}
__inline INT DM_StopTest(PCHAR s)
{
return (1);
}
__inline VOID DM_FinishTest(PCHAR test)
{
}
__inline VOID DM_Printf(PCHAR fmt, ...)
{
}
__inline VOID DM_Message(PCHAR msg)
{
}
__inline VOID DM_Status(PCHAR msg)
{
}
__inline INT DM_GetKey(VOID)
{
return (0);
}
__inline UINT Platform_IsSwitch(UCHAR sw)
{
return (SandgateIsUserSwitch(sw));
}
__inline UINT Platform_GetSwitches()
{
return (SandgateGetUserSwitches());
}
__inline VOID Platform_FatalWriteLeds(UINT LEDbits)
{
if (expansionBoardPresent())
{
NeponsetWriteLeds(LEDbits);
WaitMs(200);
NeponsetWriteLeds(0);
WaitMs(200);
}
else
{
SandgateSetRedLed();
WaitMs(200);
SandgateClearRedLed();
WaitMs(200);
}
}
__inline VOID Platform_FatalSetLeds(UINT LEDbit)
{
UINT count = 1 << LEDbit;
do
{
SandgateSetRedLed();
WaitMs(200);
SandgateClearRedLed();
WaitMs(200);
}
while (count--);
}
__inline PCHAR GetSandgateWhoAmI(BOOL flag)
{
if (flag)
{
return "PXA270 Installed";
}
else
{
return "RBBUL";
}
}
__inline PCHAR GetNeponsetWhoAmI()
{
if (expansionBoardPresent())
{
return "SA-1111 Companion board";
}
else
{
return "No Expansion board";
}
}
__inline PCHAR XsClockRateString()
{
switch (GetCCCR())
{
case CORE_CLK_195_195_MHZ: // Run Mode: 195 MHZ, Turbo Mode: 195 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "195 MHZ - Turbo Mode";
}
else
{
return "195 MHZ - Run Mode";
}
case CORE_CLK_195_487_MHZ: // Run Mode: 195 MHZ, Turbo Mode: 487 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "487 MHZ - Turbo Mode";
}
else
{
return "195 MHZ - Run Mode";
}
case CORE_CLK_208_208_MHZ: // Run Mode: 208 MHZ, Turbo Mode: 208 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "208 MHZ - Turbo Mode";
}
else
{
return "208 MHZ - Run Mode";
}
case CORE_CLK_208_520_MHZ: // Run Mode: 208 MHZ, Turbo Mode: 520 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "520 MHZ - Turbo Mode";
}
else
{
return "208 MHZ - Run Mode";
}
}
return "";
}
__inline PCHAR XsMemoryRateString()
{
UINT hwConfig = GetHWConfig();
if (hwConfig & HWConfig_BusSPEED)
{
return "50 MHZ";
}
else
{
return "100 MHZ";
}
}
__inline PCHAR GetCpuTrademark()
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_TRADEMARK(CpuVersion))
{
case 0x69:
return "Intel Corporation";
default:
return "";
}
}
__inline PCHAR GetCpuArchitecture()
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_ARCH_VER(CpuVersion))
{
case 0x05:
return "ARM Architecture version 5TE";
default:
return "";
}
}
__inline PCHAR GetCpuCoreGeneration()
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_CORE_GEN(CpuVersion))
{
case 0x01:
return "Intel(T) XScale(TM) Microarchitecture";
default:
return "";
}
}
__inline PCHAR GetCpuCoreRevision()
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_CORE_REV(CpuVersion))
{
case 0x0: // A0,A1
case 0x2: // B0,B1,B2,C0
return "First version";
default:
return "";
}
}
__inline PCHAR GetCpuProductNumber(BOOL flag)
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_PRODUCT_NUM(CpuVersion))
{
case 0x11: // PXA270
return "PXA270 Application Processor";
default:
return "";
}
}
__inline PCHAR GetCpuProductRevision(BOOL flag)
{
UINT CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_PRODUCT_REV(CpuVersion))
{
case STEP_A0:
if (flag)
{
return "A0 Stepping";
}
else
{
return "A0";
}
case STEP_A1:
if (flag)
{
return "A1 Stepping";
}
else
{
return "A1";
}
case STEP_B0:
if (flag)
{
return "B0 Stepping";
}
else
{
return "B0";
}
case STEP_C0:
if (flag)
{
return "C0 Stepping";
}
else
{
return "C0";
}
default:
return "";
}
}
__inline PCHAR GetMMUConfiguration()
{
if (IsMMUEnabled())
{
if (IsICacheEnabled())
{
if (IsDCacheEnabled())
{
return "MMU, ICache, DCache on";
}
else
{
return "MMU, ICache on";
}
}
else
{
return "MMU on";
}
}
else
{
return "MMU off";
}
}
// Allocate a memory block from the cached heap.
__inline PVOID malloc(UINT32 size)
{
return ((PVOID)0xA0400000);
}
// Allocate a memory block from the cached heap.
__inline UINT32 mallocx(UINT32 size, void **virtualAddr, void **physicalAddr)
{
return (0);
}
__inline void free(PVOID virtualAddr)
{
}
__inline UINT32 freex(PVOID virtualAddr)
{
return (0);
}
#endif // _post_h_
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