setup.h

pxa270 的bootloader源码

#include <types.h>

#ifndef _STATUS_H
#define _STATUS_H

#define MYIPADDR				"192.168.0.1"  //0x0200a8c0
#define DESTIPADDR				"192.168.0.50" //0x6400a8c0
#define MYHADDR				{0x00,0x0b,0xf3,0xaf,0xea,0xb6}
#define AUTOBOOT				"load kernel; load ramdisk; boot"
#define KERNEL					"zImage_qt"
#define FILESYSTEM				"rootfs270qt.img"
#define DELAYTIME				2

struct setup_t {
	uint32 sid;
	uint32 size;
	uint32 myipaddr;
	uint32 destipaddr;
	uchar  myhaddr[8];
	uchar  autoboot[0x100];
	uchar  kernelname[40];
	uchar  fsname[40];
	uint32 delay;
};

struct map {
	const char *name;
	ulong sramb;		/* static memeory base */
	ulong srams;		/* static memeory size */
	ulong dramb;		/* dynamic memeory base */
	ulong drams;		/* dynamic memeory size */
	ulong maxs;			/* max size */
};


extern struct setup_t *setup;
extern void save_setup(void);

extern struct map *find_map(const char *name);


#if __GNUC__ >= 3 && __GNUC_MINOR__ >= 3
# define __attribute_used__		__attribute__((__used__))
#else
# define __attribute_used__		__attribute__((__unused__))
#endif
#define __bsetup	__attribute_used__ __attribute__((section(".setup")))





#define PWR_I2C_REGISTER_BASE      0x40F00180
#define CKEN_REGISTER_BASE		0x41300000
#define OST_REGISTER_BASE		0x40A00000
#define PCFR_REG_BASE	0x40F0001C
#define PI2C_EN_BIT		(1 << 6) 

#define OST_TICKS_MS    3250          // 1ms in ticks (3.25x10^6tick/sec * 1/1000sec/msec)

//
// OST Register Definitions
//
typedef struct
{
    VUINT32    osmr0;         	//OS timer match register 0
    VUINT32    osmr1;         	//OS timer match register 1
    VUINT32    osmr2;         	//OS timer match register 2
    VUINT32    osmr3;          	//OS timer match register 3
    VUINT32    oscr0;            //OS timer counter register 0(compatible)
    VUINT32    ossr;             //OS timer status register
    VUINT32    ower;          	//OS timer watchdog enable register
    VUINT32    oier;           	//OS timer interrupt enable register
    VUINT32    osnr;           	//OS timer snapshot register
    VUINT32    reserved1[7];
    VUINT32    oscr4;		//OS timer counter register 4
    VUINT32    oscr5;		//OS timer counter register  5
    VUINT32    oscr6;		//OS timer counter register  6
    VUINT32    oscr7;		//OS timer counter register  7
    VUINT32    oscr8;		//OS timer counter register  8
    VUINT32    oscr9;		//OS timer counter register  9
    VUINT32    oscr10;		//OS timer counter register  10
    VUINT32    oscr11;		//OS timer counter register  11
    VUINT32    reserved2[8];
    VUINT32    osmr4;		//OS timer match register 4
    VUINT32    osmr5;		//OS timer match register 5
    VUINT32    osmr6;		//OS timer match register 6
    VUINT32    osmr7;		//OS timer match register 7
    VUINT32    osmr8;		//OS timer match register 8
    VUINT32    osmr9;		//OS timer match register 9
    VUINT32    osmr10;		//OS timer match register 10
    VUINT32    osmr11;		//OS timer match register 11
    VUINT32    reserved3[8];
    VUINT32    omcr4;		//OS timer match control register 4
    VUINT32    omcr5;		//OS timer match control register 5
    VUINT32    omcr6;		//OS timer match control register 6
    VUINT32    omcr7;		//OS timer match control register 7
    VUINT32    omcr8;		//OS timer match control register 8
    VUINT32    omcr9;		//OS timer match control register 9
    VUINT32    omcr10;		//OS timer match control register 10
    VUINT32    omcr11;		//OS timer match control register 11
}OST_T;


// Clock Enable Register (CLKEN) Bits
//
#define CLKEN_PWM0_2	    (0x1u << 0)
#define CLKEN_PWM1_3	    (0x1u << 1)
#define CLKEN_AC97		    (0x1u << 2)
#define CLKEN_SSP2		    (0x1u << 3)
#define CLKEN_SSP3		    (0x1u << 4)
#define CLKEN_STUART	    (0x1u << 5)
#define CLKEN_FFUART	    (0x1u << 6)
#define CLKEN_BTUART	    (0x1u << 7)
#define CLKEN_I2S		    (0x1u << 8)
#define CLKEN_OST		    (0x1u << 9)
#define CLKEN_USBHOST	    (0x1u << 10)
#define CLKEN_USBCLIENT    (0x1u << 11)
#define CLKEN_MMC		    (0x1u << 12)
#define CLKEN_ICP		    (0x1u << 13)
#define CLKEN_I2C		    (0x1u << 14)
#define CLKEN_PWRI2C	    (0x1u << 15)
#define CLKEN_LCD		    (0x1u << 16)
#define CLKEN_BASEBAND     (0x1u << 17)
#define CLKEN_USIM		    (0x1u << 18)
#define CLKEN_KEYPAD	    (0x1u << 19)
#define CLKEN_MEMCLOCK     (0x1u << 20)
#define CLKEN_MEMSTICK	    (0x1u << 21)
#define CLKEN_MEMC		    (0x1u << 22)
#define CLKEN_SSP1		    (0x1u << 23)
#define CLKEN_CAMERA	    (0x1u << 24) // Camera Capture interface
#define CLKEN_TPM		    (0x1u << 25) // Trusted Platform Module (Caddo)


typedef struct
{
    VUINT32    cccr;         	// Core Clock Configuration register
    VUINT32    cken;         	// Clock Enable register
    VUINT32    oscc;         	// Oscillator Configuration register
    VUINT32    ccsr;         	// Core Clock Status register
 }CLKMGR_T;  



typedef struct 
{
    VUINT32 ibmr;         /* Bus monitor register */
	uint32 RESERVED1;	/* addr. offset 0x84-0x88 */
	VUINT32 idbr;			/* Data buffer Register */
  	uint32 RESERVED2;	/* addr. offset 0x8C-0x90*/
  	VUINT32 icr;			/* Global Control Register */
  	uint32 RESERVED3;	/* addr. offset 0x94-0x98 */
  	VUINT32 isr;			/* Status Register*/
    uint32 RESERVED4;	/* addr. offset 0x9C-0xA0 */
  	VUINT32 isar;			/* Slave address register */
	VUINT32 pcfr;

}P_I2c_RegsT;

typedef enum 
{
    FALSE = 0, 
    TRUE = 1
}BOOL_T;


/*  bus monitor register */
#define	IBMR_SDA		( 1u << 0 )  /* reflects the status of SDA pin */
#define	IBMR_SCL		( 1u << 1 )/* reflects the status of SCL pin */

/* data buffer regiter mask */
#define	IDBR_ADDR		0xFF;  /*buffer for I2C bus send/receive data */
#define	IDBR_MODE		( 1u << 0 )	

extern void OstDelayMilliSeconds (uint32 milliseconds);
extern void OstDelayTicks(uint32 ticks);
extern BOOL_T I2CWrite(uint8 theReg, uint8 data);
#endif