can.c

Luminary cotex-M3 CAN总线 源代码

    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));
    ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);

    //
    // Enable the specified interrupts.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) | ulIntFlags);
}

//*****************************************************************************
//
//! Disables individual CAN controller interrupt sources.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the specified CAN controller interrupt sources.  Only enabled
//! interrupt sources can cause a processor interrupt.
//!
//! The parameter \e ulIntFlags has the same definition as in the function
//! CANIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));
    ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);

    //
    // Disable the specified interrupts.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) & ~(ulIntFlags));
}

//*****************************************************************************
//
//! Returns the current CAN controller interrupt status.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param eIntStsReg indicates which interrupt status register to read
//!
//! Returns the value of one of two interrupt status registers.  The
//! interrupt status register read is determined by the parameter
//! \e eIntStsReg, which can have one of the following values:
//! - CAN_INT_STS_CAUSE - indicates the cause of the interrupt
//! - CAN_INT_STS_OBJECT - indicates pending interrupts of all message objects
//!
//! CAN_INT_STS_CAUSE returns the value of the controller interrupt register
//! and indicates the cause of the interrupt.  It will be a value of
//! CAN_INT_INTID_STATUS if the cause is a status interrupt.  In this case,
//! the status register should be read with the CANStatusGet() function.
//! Calling this function to read the status will also clear the status
//! interrupt.  If the value of the interrupt register is in the range 1-32,
//! then this indicates the number of the highest priority message object that
//! has an interrupt pending. The message object interrupt can be cleared by
//! using the CANIntClear() function, or by reading the message using
//! CANMessageGet() in the case of a received message.  The interrupt handler
//! can read the interrupt status again to make sure all pending interrupts are
//! cleared before returning from the interrupt.
//!
//! CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
//! have pending interrupts.  This can be used to discover all of the
//! pending interrupts at once, as opposed to repeatedly reading the interrupt
//! register by using CAN_INT_STS_CAUSE.
//!
//! \return The value of one of the interrupt status registers.
//
//*****************************************************************************
unsigned long
CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
{
    unsigned long ulStatus;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // See which status the caller is looking for.
    //
    switch(eIntStsReg)
    {
        //
        // The caller wants the global interrupt status for the CAN controller
        // specified by ulBase.
        //
        case CAN_INT_STS_CAUSE:
        {
            ulStatus = CANReadReg(ulBase + CAN_O_INT);
            break;
        }

        //
        // The caller wants the current message status interrupt for all
        // messages.
        //
        case CAN_INT_STS_OBJECT:
        {
            //
            // Read and combine both 16 bit values into one 32bit status.
            //
            ulStatus = (CANReadReg(ulBase + CAN_O_MSGINT1) &
                        CAN_MSGINT1_INTPND);
            ulStatus |= (CANReadReg(ulBase + CAN_O_MSGINT2) << 16);
            break;
        }

        //
        // Request was for unknown status so just return 0.
        //
        default:
        {
            ulStatus = 0;
            break;
        }
    }
    //
    // Return the interrupt status value
    //
    return(ulStatus);
}

//*****************************************************************************
//
//! This call is used to clears a CAN interrupt source.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param ulIntClr is a value indicating which interrupt source to clear
//!
//! This function can be used to clear a specific interrupt source.  The
//! parameter \e ulIntClr should be one of the following values:
//! - CAN_INT_INTID_STATUS - Clears a status interrupt.
//! - 1-32 - Clear the specified message object interrupt
//!
//! It is not necessary to use this function to clear an interrupt.  This
//! should only be used if the application wants to clear an interrupt source
//! without taking the normal interrupt action.
//!
//! Normally, the status interrupt is cleared by reading the controller status,
//! by calling CANStatusGet().  A specific message object interrupt is normally
//! cleared by reading the message object (see CANMessageGet()).
//!
//! \return None.
//
//*****************************************************************************
void
CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));
    ASSERT((ulIntClr == CAN_INT_INTID_STATUS) ||
           ((ulIntClr>=1) && (ulIntClr <=32)));

    if(ulIntClr == CAN_INT_INTID_STATUS)
    {
        //
        // Simply read and discard the status to clear the interrupt.
        //
        CANReadReg(ulBase + CAN_O_STS);
    }
    else
    {
        //
        // Wait to be sure that this interface is not busy.
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }

        //
        // Only change the interrupt pending state by setting only the
        // CAN_IFCMSK_CLRINTPND bit.
        //
        CANWriteReg(ulBase + CAN_O_IF1CMSK, CAN_IFCMSK_CLRINTPND);

        //
        // Send the clear pending interrupt command to the CAN controller.
        //
        CANWriteReg(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IFCRQ_MNUM_MSK);

        //
        // Wait to be sure that this interface is not busy.
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }
    }
}

//*****************************************************************************
//
//! Sets the CAN controller auto-retransmission behavior.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param bAutoRetry enables auto-retransmission
//!
//! Enables or disables automatic retransmission of messages with detected
//! errors.  If \e bAutoRetry is \b true, then auto-retransmission is enabled,
//! otherwise it is disabled.
//!
//! \return None.
//
//*****************************************************************************
void
CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry)
{
    unsigned long ulCtlReg;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    ulCtlReg = CANReadReg(ulBase + CAN_O_CTL);

    //
    // Conditionally set the DAR bit to enable/disable auto-retry.
    //
    if(bAutoRetry)
    {
        //
        // Clearing the DAR bit tells the controller to not disable the
        // auto-retry of messages which were not transmited or received
        // correctly.
        //
        ulCtlReg &= ~CAN_CTL_DAR;
    }
    else
    {
        //
        // Setting the DAR bit tells the controller to disable the auto-retry
        // of messages which were not transmited or received correctly.
        //
        ulCtlReg |= CAN_CTL_DAR;
    }

    CANWriteReg(ulBase + CAN_O_CTL, ulCtlReg);
}

//*****************************************************************************
//
//! Returns the current setting for auto-retransmission.
//!
//! \param ulBase is the base address of the CAN controller.
//!
//! Reads the current setting of the auto-retransmission setting in the CAN
//! controller and returns it to the caller.
//!
//! \return \b true if automatic retransmission is enabled, \b false otherwise.
//
//*****************************************************************************
tBoolean
CANRetryGet(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    //
    // Read the disable automatic retry setting from the CAN controller.
    //
    if(CANReadReg(ulBase + CAN_O_CTL) & CAN_CTL_DAR)
    {
        //
        // Automatic data retransmission is not enabled.
        //
        return(false);
    }

    //
    // Automatic data retransmission is enabled.
    //
    return(true);
}

//*****************************************************************************
//
//! Reads one of the controller status registers.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param eStatusReg is the status register to read
//!
//! Reads a status register of the CAN controller and returns it to the
//! caller.  The different status registers are:
//!
//! - CAN_STS_CONTROL - the main controller status
//! - CAN_STS_TXREQUEST - bit mask of objects pending transmission
//! - CAN_STS_NEWDAT - bit mask of objects with new data
//! - CAN_STS_MSGVAL - bit mask of objects with valid configuration
//!
//! When reading the main controller status register, a pending status
//! interrupt will be cleared.  This should be used in the interrupt handler
//! for the CAN controller if the cause is a status interrupt.  The fields of
//! controller status register are as follows:
//!
//! - CAN_STS_BOFF - controller is in bus-off condition
//! - CAN_STS_EWARN - an error counter has reached a limit of at least 96
//! - CAN_STS_EPASS - CAN controller is in the error passive state
//! - CAN_STS_RXOK - a message was received successfully (independent of
//! any message filtering.
//! - CAN_STS_TXOK - a message was successfully transmitted
//! - CAN_STS_LEC_MSK - mask of last error code bits (3 bits)
//! - CAN_STS_LEC_NONE - no error
//! - CAN_STS_LEC_STUFF - stuffing error detected
//! - CAN_STS_LEC_FORM - a format error in the fixed format part of a message
//! - CAN_STS_LEC_ACK - a transmitted message was not acknowledged
//! - CAN_STS_LEC_BIT1 - dominant level detected when trying to send recessive
//! - CAN_STS_LEC_BIT0 - recessive level detected when trying to send dominant
//! - CAN_STS_LEC_CRC - CRC error in received message
//!
//! The remaining status registers are 32-bit bit maps to the message
//! objects. They can be used to quickly obtain information about the status
//! of all the message object without needing to query each one.  They contain
//! the following information:
//!
//! - CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that
//! means that a transmission is pending on that object.  The application
//! can use this to determine which objects are still waiting to send a
//! message.
//! - CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means
//! that a new message has been received in that object, and has not yet
//! been picked up by the host application
//! - CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means
//! it has a valid configuration programmed.  The host application can use
//! this to determine which message objects are empty/unused.
//!
//! \return The value of the status register.
//
//*****************************************************************************
unsigned long
CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg)
{
    unsigned long ulStatus;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE));

    switch (eStatusReg)
    {
        //
        // Just return the global CAN status register since that is what was
        // requested.
        //
        case CAN_STS_CONTROL:
        {
            ulStatus = CANReadReg(ulBase + CAN_O_STS);
            CANWriteReg(
                ulBase + CAN_O_STS,
                ~(CAN_STS_RXOK | CAN_STS_TXOK | CAN_STS_LEC_MSK));
            break;
        }

        //
        // Combine the Transmit status bits into one 32bit value.
        //
        case CAN_STS_TXREQUEST:
        {
            ulStatus = CANReadReg(ulBase + CAN_O_TXRQ1);
            ulStatus |= CANReadReg(ulBase + CAN_O_TXRQ2) << 16;
            break;
        }

        //
        // Combine the New Data status bits into one 32bit value.
        //
        case CAN_STS_NEWDAT:
        {
            ulStatus = CANReadReg(ulBase + CAN_O_NWDA1);
            ulStatus |= CANReadReg(ulBase + CAN_O_NWDA2) << 16;
            break;
        }