lm3s1332.h
来自「Luminary coxter_M3 内核的遥控源代码」· C头文件 代码 · 共 1,089 行 · 第 1/5 页
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#define UART_CTL_RXE 0x00000200 // UART Receive Enable.
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable.
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable.
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low Power Mode.
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable.
#define UART_CTL_UARTEN 0x00000001 // UART Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select.
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO <= 1/8 full
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO <= 1/4 full
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO <= 1/2 full (default)
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO <= 3/4 full
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO <= 7/8 full
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select.
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO >= 1/8 full
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO >= 1/4 full
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO >= 1/2 full (default)
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO >= 3/4 full
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO >= 7/8 full
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask.
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask.
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt
// Mask.
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask.
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask.
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask.
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status.
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status.
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status.
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status.
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status.
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status.
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status.
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status.
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status.
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status.
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status.
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status.
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear.
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear.
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear.
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear.
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt
// Clear.
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear.
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration.
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration.
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration.
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode
// Select.
#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode
// Select.
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM TimerB PWM Output Level.
#define TIMER_CTL_TBOTE 0x00002000 // GPTM TimerB Output Trigger
// Enable.
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge.
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge.
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges.
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM TimerB Stall Enable.
#define TIMER_CTL_TBEN 0x00000100 // GPTM TimerB Enable.
#define TIMER_CTL_TAPWML 0x00000040 // GPTM TimerA PWM Output Level.
#define TIMER_CTL_TAOTE 0x00000020 // GPTM TimerA Output Trigger
// Enable.
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable.
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge.
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge.
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges.
#define TIMER_CTL_TASTALL 0x00000002 // GPTM TimerA Stall Enable.
#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_CBEIM 0x00000400 // GPTM CaptureB Event Interrupt
// Mask.
#define TIMER_IMR_CBMIM 0x00000200 // GPTM CaptureB Match Interrupt
// Mask.
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM TimerB Time-Out Interrupt
// Mask.
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask.
#define TIMER_IMR_CAEIM 0x00000004 // GPTM CaptureA Event Interrupt
// Mask.
#define TIMER_IMR_CAMIM 0x00000002 // GPTM CaptureA Match Interrupt
// Mask.
#define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt
// Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_CBERIS 0x00000400 // GPTM CaptureB Event Raw
// Interrupt.
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM CaptureB Match Raw
// Interrupt.
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM TimerB Time-Out Raw
// Interrupt.
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt.
#define TIMER_RIS_CAERIS 0x00000004 // GPTM CaptureA Event Raw
// Interrupt.
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM CaptureA Match Raw
// Interrupt.
#define TIMER_RIS_TATORIS 0x00000001 // GPTM TimerA Time-Out Raw
// Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked
// Interrupt.
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked
// Interrupt.
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked
// Interrupt.
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked
// Interrupt.
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked
// Interrupt.
#define TIMER_MIS_TATOMIS ⌨️ 快捷键说明
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