lm3s610.h

来自「Luminary coxter_M3 内核的遥控源代码」· C头文件 代码 · 共 1,128 行 · 第 1/5 页

#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
#define I2C_SCSR_DA             0x00000001  // Device Active.
#define I2C_SCSR_RREQ           0x00000001  // Receive Request.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
#define I2C_MCS_STOP            0x00000004  // Generate STOP.
#define I2C_MCS_START           0x00000002  // Generate START.
#define I2C_MCS_ERROR           0x00000002  // Error.
#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
#define I2C_MCS_BUSY            0x00000001  // I2C Busy.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
#define I2C_SDR_DATA_S          0

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
#define I2C_MDR_DATA_S          0

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
#define I2C_MTPR_TPR_S          0

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_IM             0x00000001  // Interrupt Mask.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_IC             0x00000001  // Clear Interrupt.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_IC             0x00000001  // Interrupt Clear.

//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_CTL register.
//
//*****************************************************************************
#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_SYNC register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter.
#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter.
#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENABLE register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable.
#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable.
#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable.
#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable.
#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable.
#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INVERT register.
//
//*****************************************************************************
#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal.
#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal.
#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal.
#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal.
#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal.
#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULT register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Driven Low on Fault.
#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Driven Low on Fault.
#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Driven Low on Fault.
#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Driven Low on Fault.
#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Driven Low on Fault.
#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Driven Low on Fault.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INTEN register.
//
//*****************************************************************************
#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_RIS register.
//
//*****************************************************************************
#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ISC register.
//
//*****************************************************************************
#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_STATUS register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_CTL,
// PWM_O_1_CTL, and PWM_O_2_CTL registers.
//
//*****************************************************************************
#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode.
#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode.
#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode.
#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode.
#define PWM_X_CTL_MODE          0x00000002  // Counter Mode.
#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_INTEN,
// PWM_O_1_INTEN, and PWM_O_2_INTEN registers.
//
//*****************************************************************************
#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=Comparator B
                                            // Down.
#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=Co