📄 hw_sysctl.h
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#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
//
//*****************************************************************************
#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.
#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.
#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.
#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.
#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.
#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.
#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.
#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.
#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.
#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.
#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.
#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.
#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.
#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.
#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.
#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
//
//*****************************************************************************
#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.
#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.
#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.
#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.
#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.
#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.
#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.
#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.
#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.
#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RIS register.
//
//*****************************************************************************
#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.
#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
// Status.
#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
// Interrupt Status.
#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
// Interrupt Status.
#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
// Interrupt Status.
#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
// Status.
#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_IMC register.
//
//*****************************************************************************
#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.
#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask.
#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
// Interrupt Mask.
#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
// Mask.
#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
// Mask.
#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.
#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_MISC register.
//
//*****************************************************************************
#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt
// Status.
#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
// Status.
#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
// Interrupt Status.
#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
// Interrupt Status.
#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
// Interrupt Status.
#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
//
//*****************************************************************************
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
//
//*****************************************************************************
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
// Gating.
#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
// Gating.
#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
//
//*****************************************************************************
#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
//
//*****************************************************************************
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.
#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
//
//*****************************************************************************
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock
// Gating.
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock
// Gating.
#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock
// Gating.
#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.
#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.
#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.
#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.
#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.
#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.
#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.
#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.
#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.
#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.
#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
//
//*****************************************************************************
#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.
#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.
#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.
#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.
#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.
#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.
#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
//
//*****************************************************************************
#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.
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