lm3s315.h

来自「Luminary coxter_M3 内核的遥控源代码」· C头文件代码 · 共 1,126 行 · 第 1/5 页
1,126 行

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//*****************************************************************************
#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty.
#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full.
#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full.
#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty.
#define UART_FR_BUSY            0x00000008  // UART Busy.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
#define UART_IBRD_DIVINT_S      0

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
#define UART_FBRD_DIVFRAC_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
#define UART_LCRH_BRK           0x00000001  // UART Send Break.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//*****************************************************************************
#define UART_CTL_RXE            0x00000200  // UART Receive Enable.
#define UART_CTL_TXE            0x00000100  // UART Transmit Enable.
#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable.
#define UART_CTL_UARTEN         0x00000001  // UART Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
                                            // Level Select.
#define UART_IFLS_RX1_8         0x00000000  // RX FIFO <= 1/8 full
#define UART_IFLS_RX2_8         0x00000008  // RX FIFO <= 1/4 full
#define UART_IFLS_RX4_8         0x00000010  // RX FIFO <= 1/2 full (default)
#define UART_IFLS_RX6_8         0x00000018  // RX FIFO <= 3/4 full
#define UART_IFLS_RX7_8         0x00000020  // RX FIFO <= 7/8 full
#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
                                            // Level Select.
#define UART_IFLS_TX1_8         0x00000000  // TX FIFO >= 1/8 full
#define UART_IFLS_TX2_8         0x00000001  // TX FIFO >= 1/4 full
#define UART_IFLS_TX4_8         0x00000002  // TX FIFO >= 1/2 full (default)
#define UART_IFLS_TX6_8         0x00000003  // TX FIFO >= 3/4 full
#define UART_IFLS_TX7_8         0x00000004  // TX FIFO >= 7/8 full

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
                                            // Mask.
#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask.
#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt
                                            // Mask.
#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
                                            // Mask.
#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
                                            // Mask.
#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask.
#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
                                            // Status.
#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
                                            // Status.
#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
                                            // Status.
#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
                                            // Status.
#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
                                            // Interrupt Status.
#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
                                            // Status.
#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
                                            // Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
                                            // Interrupt Status.
#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
                                            // Interrupt Status.
#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
                                            // Interrupt Status.
#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
                                            // Interrupt Status.
#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
                                            // Interrupt Status.
#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
                                            // Status.
#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
                                            // Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear.
#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear.
#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear.
#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear.
#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt
                                            // Clear.
#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear.
#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_CTL register.
//
//*****************************************************************************
#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_SYNC register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENABLE register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable.
#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INVERT register.
//
//*****************************************************************************
#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal.
#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULT register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Driven Low on Fault.
#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Driven Low on Fault.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INTEN register.
//
//*****************************************************************************
#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_RIS register.
//
//*****************************************************************************
#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ISC register.
//
//*****************************************************************************
#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_STATUS register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status.

//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_0_CTL register.
//
//*****************************************************************************
#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode.
#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode.
#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode.
#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode.
#define PWM_X_CTL_MODE          0x00000002  // Counter Mode.
#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable.
lm3s315.h - 源码说明

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