hw_uart.h

Luminary coxter_M3 内核的遥控源代码

//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware
//
// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved.
// 
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 1928 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

#ifndef __HW_UART_H__
#define __HW_UART_H__

//*****************************************************************************
//
// The following are defines for the UART Register offsets.
//
//*****************************************************************************
#define UART_O_DR               0x00000000  // Data Register
#define UART_O_RSR              0x00000004  // Receive Status Register (read)
#define UART_O_ECR              0x00000004  // Error Clear Register (write)
#define UART_O_FR               0x00000018  // Flag Register (read only)
#define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
#define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg
#define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg
#define UART_O_LCRH             0x0000002C  // UART Line Control
#define UART_O_CTL              0x00000030  // Control Register
#define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg
#define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg
#define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register
#define UART_O_MIS              0x00000040  // Masked Interrupt Status Register
#define UART_O_ICR              0x00000044  // Interrupt Clear Register

//*****************************************************************************
//
// The following are defines for the Data Register bits
//
//*****************************************************************************
#define UART_DR_OE              0x00000800  // Overrun Error
#define UART_DR_BE              0x00000400  // Break Error
#define UART_DR_PE              0x00000200  // Parity Error
#define UART_DR_FE              0x00000100  // Framing Error
#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
#define UART_DR_DATA_S          0

//*****************************************************************************
//
// The following are defines for the Receive Status Register bits
//
//*****************************************************************************
#define UART_RSR_OE             0x00000008  // Overrun Error
#define UART_RSR_BE             0x00000004  // Break Error
#define UART_RSR_PE             0x00000002  // Parity Error
#define UART_RSR_FE             0x00000001  // Framing Error

//*****************************************************************************
//
// The following are defines for the Flag Register bits
//
//*****************************************************************************
#define UART_FR_TXFE            0x00000080  // TX FIFO Empty
#define UART_FR_RXFF            0x00000040  // RX FIFO Full
#define UART_FR_TXFF            0x00000020  // TX FIFO Full
#define UART_FR_RXFE            0x00000010  // RX FIFO Empty
#define UART_FR_BUSY            0x00000008  // UART Busy

//*****************************************************************************
//
// The following are defines for the Integer baud-rate divisor
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
#define UART_IBRD_DIVINT_S      0

//*****************************************************************************
//
// The following are defines for the Fractional baud-rate divisor
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
#define UART_FBRD_DIVFRAC_S     0

//*****************************************************************************
//
// The following are defines for the Control Register bits
//
//*****************************************************************************
#define UART_CTL_RXE            0x00000200  // Receive Enable
#define UART_CTL_TXE            0x00000100  // Transmit Enable
#define UART_CTL_LBE            0x00000080  // Loopback Enable
#define UART_CTL_SIRLP          0x00000004  // SIR (IrDA) Low Power Enable
#define UART_CTL_SIREN          0x00000002  // SIR (IrDA) Enable
#define UART_CTL_UARTEN         0x00000001  // UART Enable

//*****************************************************************************
//
// The following are defines for the Interrupt FIFO Level Select Register bits
//
//*****************************************************************************
#define UART_IFLS_RX_M          0x00000038  // RX FIFO Level Interrupt Mask
#define UART_IFLS_RX1_8         0x00000000  // 1/8 Full
#define UART_IFLS_RX2_8         0x00000008  // 1/4 Full
#define UART_IFLS_RX4_8         0x00000010  // 1/2 Full
#define UART_IFLS_RX6_8         0x00000018  // 3/4 Full
#define UART_IFLS_RX7_8         0x00000020  // 7/8 Full
#define UART_IFLS_TX_M          0x00000007  // TX FIFO Level Interrupt Mask
#define UART_IFLS_TX1_8         0x00000000  // 1/8 Full
#define UART_IFLS_TX2_8         0x00000001  // 1/4 Full
#define UART_IFLS_TX4_8         0x00000002  // 1/2 Full
#define UART_IFLS_TX6_8         0x00000003  // 3/4 Full
#define UART_IFLS_TX7_8         0x00000004  // 7/8 Full

//*****************************************************************************
//
// The following are defines for the Interrupt Mask Set/Clear Register bits
//
//*****************************************************************************
#define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask
#define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask
#define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask
#define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask
#define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask
#define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask
#define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask

//*****************************************************************************
//
// The following are defines for the Raw Interrupt Status Register
//
//*****************************************************************************
#define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status
#define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status
#define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status
#define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status
#define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status
#define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status
#define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status

//*****************************************************************************
//
// The following are defines for the Masked Interrupt Status Register
//
//*****************************************************************************
#define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status
#define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status
#define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status
#define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status
#define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status