📄 lm3s301.h
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#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060))
#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064))
#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068))
#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070))
//*****************************************************************************
//
// General-Purpose Timers (TIMER0)
//
//*****************************************************************************
#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
//*****************************************************************************
//
// General-Purpose Timers (TIMER1)
//
//*****************************************************************************
#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
//*****************************************************************************
//
// Analog-to-Digital Converter (ADC)
//
//*****************************************************************************
#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
#define ADC_RIS_R (*((volatile unsigned long *)0x40038004))
#define ADC_IM_R (*((volatile unsigned long *)0x40038008))
#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C))
#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010))
#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014))
#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018))
#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020))
#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028))
#define ADC_SAC_R (*((volatile unsigned long *)0x40038030))
#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040))
#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044))
#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060))
#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064))
#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080))
#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084))
#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100))
//*****************************************************************************
//
// Analog Comparators (COMP)
//
//*****************************************************************************
#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
//*****************************************************************************
//
// Internal Memory (FLASH)
//
//*****************************************************************************
#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
#define FLASH_FMPRE_R (*((volatile unsigned long *)0x400FE130))
#define FLASH_FMPPE_R (*((volatile unsigned long *)0x400FE134))
#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140))
//*****************************************************************************
//
// System Control (SYSCTL)
//
//*****************************************************************************
#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034))
#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
#define SYSCTL_CLKVCLR_R (*((volatile unsigned long *)0x400FE150))
#define SYSCTL_LDOARST_R (*((volatile unsigned long *)0x400FE160))
//*****************************************************************************
//
// Nested Vectored Interrupt Ctrl (NVIC)
//
//*****************************************************************************
#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//*****************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.
#define WDT_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//*****************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.
#define WDT_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//*****************************************************************************
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable.
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable.
//*****************************************************************************
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