📄 helper.c
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#include <stdio.h>#include <unistd.h>#include <string.h>#define ALLOW_OS_CODE 1#include "rmdef/rmdef.h"#include "llad/include/gbus.h"#include "emhwlib_hal/i2c/include/i2c_hal.h"#include "emhwlib_hal/include/emhwlib_registers.h"//#define GPIO_DIR_ADDR (REG_BASE_system_block + SYS_gpio_dir)//#define GPIO_DATA_ADDR (REG_BASE_system_block + SYS_gpio_data)#include "helper.h"typedef struct tagPioRegisterConfiguration { RMuint32 uRegBase; RMuint32 uDirOffset; RMuint32 uDataOffset; RMuint32 uMask;} PIO_REG_CONFIG_T;// If the uarts are used for GPIOs, it must be configured in the Kernel.// Under Character devices.// There, it writes to the UART mode register//// GPIO pin numbers are in the HELP section of the menuconfig, when you select FULL/Partial functionality for the UART// but I will list the pin numbers here anyway://// 0 - RX 4 - TX// 1 - CTS 5 - RTS// 2 - DSR 6 - DTR// 3 - DCDtypedef enum { gpio = 0, uart0, uart1 } GPIOCFG_LISTINDEX_N;PIO_REG_CONFIG_T g_listPioRegConfig_T[] = { { REG_BASE_system_block, SYS_gpio_dir, SYS_gpio_data, 0x00010000 }, { REG_BASE_cpu_block, CPU_UART0_base + 0x30, CPU_UART0_base + 0x34, 0x0100}, { REG_BASE_cpu_block, CPU_UART1_base + 0x30, CPU_UART1_base + 0x34, 0x0100}};//RMstatus GetGpioCfgIndex(GPIO_CONFIG *pC, GPIOCFG_LISTINDEX_N *pIndex, RMuint8 pin);static RMstatus GetGpioCfgIndex(GPIO_CONFIG *pC, GPIOCFG_LISTINDEX_N *pIndex, RMuint8 pin){ assert(pC != NULL); assert( pIndex != NULL ); switch(pC->nGpioCfg) { case GpioCfg_Gpio: if( pin >= 16 ) { DPRINT(("GetGpioCfgIndex() bad pin number\n")); return RM_INVALID_PARAMETER; } *pIndex = gpio; break; case GpioCfg_Uart0: if( pin >= 6 ) { DPRINT(("GetGpioCfgIndex() bad pin number\n")); return RM_INVALID_PARAMETER; } *pIndex = uart0; break; case GpioCfg_Uart1: if( pin >= 6 ) { DPRINT(("GetGpioCfgIndex() bad pin number\n")); return RM_INVALID_PARAMETER; } *pIndex = uart1; break; default: DPRINT(("GetGpioCfgIndex() unsupported configuration\n")); return RM_INVALID_PARAMETER; } return RM_OK;}//// Exported Functions//------------------------------------------------------------------------------/* 86xx calls */RMvoid mum_exit( RMvoid* pGBus, struct llad* pLLAD ){ assert( pGBus != NULL ); assert( pLLAD != NULL ); gbus_close(pGBus); llad_close(pLLAD);}RMstatus mum_init( RMuint8 nChip, struct llad** ppLLAD, RMvoid** ppGBus){ RMascii device[10]; /* use the correct chip in the system, if provided */ assert(nChip < 16); snprintf(device, 10, "%d", nChip); *ppLLAD = llad_open(device); if( *ppLLAD == NULL ) { DPRINT(("mum_init !llad_open failed\n")); return RM_ERROR; } *ppGBus = gbus_open(*ppLLAD); if( *ppGBus == NULL ) { llad_close(*ppLLAD); return RM_ERROR; } return RM_OK;}/*RMstatus mum_i2c_sendtable( struct i2c *pI2c, RMuint8 *pData, RMuint32 uByteCount){ RMuint32 uCount; assert(pI2c != NULL); assert(pData != NULL); assert(uByteCount%2 == 0); assert(uByteCount != 0); if( pI2c->RegBase == 0) MPRINT(("WARNING, i2c Reg Base = 0\n")); DPRINT(("mum_i2c_sendtable - attempt to send %d bytes\n", uByteCount)); for( uCount = 0; uCount < uByteCount; uCount+=2 ) { if( RMFAILED(I2C_Write(pI2c, pData[uCount], pData+uCount+1, 1)) ) { DPRINT(("mum_i2c_sendtable - mum_i2c_sendtable error at Count %d\n", uCount)); return RM_ERROR; } } return RM_OK;}*/RMstatus mum_gpioSet(GPIO_CONFIG* pC, RMuint8 pin, RMuint8 high){ RMstatus s; GPIOCFG_LISTINDEX_N nIndex; assert(pC != NULL); if( (s= GetGpioCfgIndex(pC, &nIndex, pin)) != RM_OK ) return s; // in standalone mode, you can just dereference the addresses using * // I use gbus_write_uint32 to maintain compatability if(high) gbus_write_uint32(pC->pGBus, g_listPioRegConfig_T[nIndex].uRegBase + g_listPioRegConfig_T[nIndex].uDataOffset, (g_listPioRegConfig_T[nIndex].uMask |1) << pin); else gbus_write_uint32(pC->pGBus, g_listPioRegConfig_T[nIndex].uRegBase + g_listPioRegConfig_T[nIndex].uDataOffset, g_listPioRegConfig_T[nIndex].uMask << pin); return RM_OK;}RMstatus mum_gpioGet(GPIO_CONFIG* pC, RMuint8 pin, RMuint8* pData){ RMstatus s; GPIOCFG_LISTINDEX_N nIndex; assert(pC != NULL); assert(pData != NULL); if( (s= GetGpioCfgIndex(pC, &nIndex, pin)) != RM_OK ) return s; *pData = (gbus_read_uint32(pC->pGBus, g_listPioRegConfig_T[nIndex].uRegBase + g_listPioRegConfig_T[nIndex].uDataOffset) & (1 << pin))?1:0; return RM_OK;}RMstatus mum_gpioSetDir(GPIO_CONFIG* pC, RMuint8 pin, RMuint8 out){ RMstatus s; GPIOCFG_LISTINDEX_N nIndex; assert(pC != NULL); if( (s= GetGpioCfgIndex(pC, &nIndex, pin)) != RM_OK ) return s; if(out) gbus_write_uint32(pC->pGBus, g_listPioRegConfig_T[nIndex].uRegBase + g_listPioRegConfig_T[nIndex].uDirOffset, ( g_listPioRegConfig_T[nIndex].uMask | 1) << pin); else gbus_write_uint32(pC->pGBus, g_listPioRegConfig_T[nIndex].uRegBase + g_listPioRegConfig_T[nIndex].uDirOffset, g_listPioRegConfig_T[nIndex].uMask << pin); return RM_OK;}//----------------------------------------------------------------------------------------------------------RMstatus mum_sleep(RMuint32 uSeconds){ sleep(uSeconds); return RM_OK;}RMstatus mum_usleep(RMuint32 uMicroSeconds){ usleep(uMicroSeconds); return RM_OK;}//----------------------------------------------------------------------------------------------------------RMstatus I2Cal_Read_Subaddress( I2CAL_CONTEXT* pContext, RMuint8 uSlaveAddress, RMuint8 uSubAddress, RMuint8* pData, RMuint32 *pByteCount ){ RMstatus s; struct i2c i2cConfig; assert( pContext != NULL ); assert( pData != NULL ); assert( pByteCount != NULL ); assert( *pByteCount != 0 ); if( (uSlaveAddress & 0x01) == 0 ) { DPRINT(("I2Cal_Read_Subaddress() WARNING: setting iicAddr 0x%x LSB to 1\n", uSlaveAddress)); uSlaveAddress = uSlaveAddress | 0x01; } memcpy( &i2cConfig, pContext, sizeof(struct i2c) ); i2cConfig.RdAddr = uSlaveAddress; i2cConfig.WrAddr = uSlaveAddress & 0xFE; if ( (s = I2C_Read( &i2cConfig, uSubAddress, pData, *pByteCount)) != RM_OK ) { DPRINT(("I2Cal_Read_Subaddress() I2C_Read() failed %d\n", s)); *pByteCount = 0; return RM_ERROR; } return RM_OK;}RMstatus I2Cal_Write_Subaddress( I2CAL_CONTEXT* pContext, RMuint8 uSlaveAddress, RMuint8 uSubAddress, RMuint8* pData, RMuint32 *pByteCount ){ RMstatus s; struct i2c i2cConfig; assert( pContext != NULL ); assert( pData != NULL ); assert( pByteCount != NULL ); assert( *pByteCount != 0 ); if( (uSlaveAddress & 0x01) == 1 ) { DPRINT(("I2Cal_Write_Subaddress() WARNING: setting iicAddr 0x%x LSB to 0\n", uSlaveAddress)); uSlaveAddress = uSlaveAddress & 0xFE; } memcpy( &i2cConfig, pContext, sizeof(struct i2c) ); i2cConfig.WrAddr = uSlaveAddress; i2cConfig.RdAddr = uSlaveAddress | 0x01; if ( (s = I2C_Write( &i2cConfig, uSubAddress, pData, *pByteCount)) != RM_OK ) { DPRINT(("I2Cal_Write_Subaddress() I2C_Write() failed %d\n", s)); *pByteCount = 0; return RM_ERROR; } return RM_OK;}RMstatus I2Cal_Read( I2CAL_CONTEXT* pContext, RMuint8 uSlaveAddress, RMuint8* pData, RMuint32 *pByteCount ){ RMstatus s; struct i2c i2cConfig; assert( pContext != NULL ); assert( pData != NULL ); assert( pByteCount != NULL ); assert( *pByteCount != 0 ); if( (uSlaveAddress & 0x01) == 0 ) { DPRINT(("I2Cal_Read() WARNING: setting iicAddr 0x%x LSB to 1\n", uSlaveAddress)); uSlaveAddress = uSlaveAddress | 0x01; } memcpy( &i2cConfig, pContext, sizeof(struct i2c) ); i2cConfig.RdAddr = uSlaveAddress; i2cConfig.WrAddr = uSlaveAddress & 0xFE; if ( (s = I2C_Read_NoSubAddr( &i2cConfig, pData, *pByteCount)) != RM_OK ) { DPRINT(("I2Cal_Read() I2C_Read() failed %d\n", s)); *pByteCount = 0; return RM_ERROR; } return RM_OK;}RMstatus I2Cal_Write( I2CAL_CONTEXT* pContext, RMuint8 uSlaveAddress, RMuint8* pData, RMuint32 *pByteCount ){ RMstatus s; struct i2c i2cConfig; assert( pContext != NULL ); assert( pData != NULL ); assert( pByteCount != NULL ); assert( *pByteCount != 0 ); if( (uSlaveAddress & 0x01) == 1 ) { DPRINT(("I2Cal_Write() WARNING: setting iicAddr 0x%x LSB to 0\n", uSlaveAddress)); uSlaveAddress = uSlaveAddress & 0xFE; } memcpy( &i2cConfig, pContext, sizeof(struct i2c) ); i2cConfig.WrAddr = uSlaveAddress; i2cConfig.RdAddr = uSlaveAddress | 0x01; if ( (s = I2C_Write_NoSubAddr( &i2cConfig, pData, *pByteCount)) != RM_OK ) { DPRINT(("I2Cal_Write() I2C_Write_NoSubAddr() failed %d\n", s)); *pByteCount = 0; return RM_ERROR; } return RM_OK;}
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