msp34x5g.c

sigma_designs的tuner驱动

RMstatus msp34x5g_demod_getStatus(MSP34X5G_CONFIG *pC, RMuint16 *p)
{
	assert( pC != NULL );
	assert( p != NULL );	

	if( msp34x5g_readDemod(pC, msp_dmreg_status, p) != RM_OK )
		return RM_ERROR;
	
	return RM_OK;
}


RMstatus msp34x5g_demod_selectStandard(MSP34X5G_CONFIG* pC, MSP34X5G_STANDARD s)
{
	assert( pC != NULL);
	
	if( msp34x5g_writeDemod(pC, msp_dmreg_standardselect, s) != RM_OK )
		return RM_ERROR;
	
	return RM_OK;
}



RMstatus msp34x5g_demod_InputFMamPrescale(MSP34X5G_CONFIG* pC, MSP34X5G_FMamPRESCALE p)
{
	RMuint16 uCfg, data16;
	RMstatus s;

	assert( pC != NULL);

	switch( p )
	{
	case msp_fm28khz:
		uCfg = 0x7F00;
		break;
	case msp_fm50khz:
		uCfg = 0x4800;
		break;
	case msp_fm75khz:
		uCfg = 0x3000;
		break;
	case msp_fm100khz:
		uCfg = 0x2400;
		break;
	case msp_fm150khz:
		uCfg = 0x1800;
		break;
	case msp_fm180khz:
		uCfg = 0x1300;
		break;

	case msp_fm_hdev2_150khz:
		uCfg = 0x3000;
		break;
	case msp_fm_hdev2_360khz:
		uCfg = 0x1400;
		break;
		
	case msp_fm_hdev3_450khz:
		uCfg = 0x2000;
		break;
	case msp_fm_hdev3_540khz:
		uCfg = 0x1A00;
		break;
		
	case msp_fm_satellite:
		uCfg = 0x1000;
		break;

	case msp_am:
		uCfg = 0x7C00;
		break;
		
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	
	if( (s = msp34x5g_readDsp(pC, msp_dsreg_fm_premat, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_demod_InputFMamPrescale, msp34x5g_readDsp() failed %d\n", s));
		return RM_ERROR;
	}
	
	// cfg is bit 15:8
	data16 = (data16 & 0xFF) | uCfg;
	if( (s = msp34x5g_writeDsp(pC, msp_dsreg_fm_premat, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_demod_InputFMamPrescale, msp34x5g_writeDsp(data=0x%x) failed %d\n", data16, s));
		return RM_ERROR;
	}
	
	return RM_OK;
}


//
//Input: SCART1 DSP
//-------------------------------------------------------------------------------
RMstatus msp34x5g_scartdsp_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_SC_DSP_SRC src)
{
	RMuint16 data16;
	RMstatus s;

	assert( pC != NULL);

	if( (s = msp34x5g_readDsp(pC, msp_dsreg_acbreg, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_scart1dsp_SelectSource, msp34x5g_readDsp(msp_dsreg_acbreg) failed %d\n", s));
		goto msp34x5g_scart1dsp_SelectSource_error;
	}
	
	//  bit    5432 1098 7854 3210
	//  mask = 1111 1100 1101 1111
	//           xx xx00 xx0      
        //  sc_dsp_src_monoin= 0000 1000
	//  shift 5 to match bits
	data16 = data16 & 0xFCDF;
	data16 = data16 | (src << 5);
	if( (s = msp34x5g_writeDsp(pC, msp_dsreg_acbreg, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_scart1dsp_SelectSource, msp34x5g_writeDsp(msp_dsreg_acbreg, data=0x%x) failed %d\n", data16, s));
		goto msp34x5g_scart1dsp_SelectSource_error;
	}
	
	return RM_OK;
	
msp34x5g_scart1dsp_SelectSource_error:
	return RM_ERROR;
}


RMstatus msp34x5g_scartdsp_InputPrescale(MSP34X5G_CONFIG *pC, RMuint8 db)
{
	RMuint16 data16;
	RMstatus s;
	
	assert(pC != NULL);
	if( db > MSPSCARTDSP_PRESCALE_14DB )
		return RM_INVALID_PARAMETER;

	data16 = db << 8;	
	if( (s = msp34x5g_writeDsp(pC, msp_dsreg_scartdsp_prescale, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_scart1dsp_InputPrescale, msp34x5g_writeDsp(msp_dsreg_scartdsp_prescale, data=0x%x) failed %d\n", data16, s));
		return RM_ERROR;
	}
	
	return RM_OK;
}


//
// MATRIX Operations
//-------------------------------------------------------------------------------
RMstatus msp34x5g_matrix_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_MATRIX m, MSP34X5G_MATRIX_SRC src)
{
	RMuint16 data16;
	RMstatus s;
	
	assert( pC != NULL );

	switch( m )
	{
	case matrix_main:
	case matrix_sc1DA:
	case matrix_i2s:
	case matrix_qpeak:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}
	
	switch( src )
	{
	case matrix_src_demodFMAM:
	case matrix_src_stereoAB:
	case matrix_src_stereoA:
	case matrix_src_stereoB:
	case matrix_src_SCARTin:
	case matrix_src_I2S1:
	case matrix_src_I2S2:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}

	
	if( (s = msp34x5g_readDsp(pC, m, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_matrix_SelectSource, msp34x5g_readDsp(0x%x) failed %d\n", m, s));
		goto msp34x5g_matrix_SelectSource_error;
	}
	
	// source is bit 15:8
	data16 = data16 & 0xFF;
	data16 = data16 | (src << 8);
	if( (s = msp34x5g_writeDsp(pC, m, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_matrix_SelectSource, msp34x5g_writeDsp(0x%x, data=0x%x) failed %d\n", m, data16, s));
		goto msp34x5g_matrix_SelectSource_error;
	}
	
	return RM_OK;
	
msp34x5g_matrix_SelectSource_error:
	return RM_ERROR;

}



RMstatus msp34x5g_matrix_SelectMode(MSP34X5G_CONFIG *pC, MSP34X5G_MATRIX m, MSP34X5G_MATRIX_MODE md)
{
	RMuint16 data16;
	RMstatus s;
	
	assert( pC != NULL );

	switch( m )
	{
	case matrix_main:
	case matrix_sc1DA:
	case matrix_i2s:
	case matrix_qpeak:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}
	
	switch( md )
	{
	case matrix_mode_soundAMono:
	case matrix_mode_soundBMono:
	case matrix_mode_stereo:
	case matrix_mode_mono:
	case matrix_mode_sumDiff:
	case matrix_mode_abXchange:
	case matrix_mode_phaseChangeB:
	case matrix_mode_phaseChangeA:
	case matrix_mode_onlyA:
	case matrix_mode_onlyB:
		break;
	default:
		return RM_INVALID_PARAMETER;
	}

	if( (s = msp34x5g_readDsp(pC, m, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_matrix_SelectSource, msp34x5g_readDsp(0x%x) failed %d\n", m, s));
		goto msp34x5g_matrix_SelectMode_error;
	}
	
	// source is bit 15:8
	data16 = data16 & 0xFF00;
	data16 = data16 | md;
	if( (s = msp34x5g_writeDsp(pC, m, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_matrix_SelectSource, msp34x5g_writeDsp(0x%x, data=0x%x) failed %d\n", m, data16, s));
		goto msp34x5g_matrix_SelectMode_error;
	}
	
	return RM_OK;
	
msp34x5g_matrix_SelectMode_error:
	return RM_ERROR;
}


//
//Output: SCART1 OUT
//-------------------------------------------------------------------------------
RMstatus msp34x5g_scart1out_SetVolume(MSP34X5G_CONFIG *pC, RMuint8 db)
{
	RMuint16 data16;

	assert( pC != NULL );
	assert( db <= MSPVOL_MAX); // no need to check for < 0

	data16 = db << 8 | 0x01;
	return msp34x5g_writeDsp(pC, msp_dsreg_vol_scart1, data16);
}


RMstatus msp34x5g_scart1out_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_SC1OUT_SRC src)
{
	RMuint16 data16;
	RMstatus s;
	
	assert( pC != NULL );
	
	if( (s = msp34x5g_readDsp(pC, msp_dsreg_acbreg, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_scart1out_SelectSource, msp34x5g_readDsp(msp_dsreg_acbreg) failed %d\n", s));
		goto msp34x5g_scart1out_SelectSource_error;
	}
	
	//  bit    5432 1098 7854 3210
	//  mask = 1111 0011 1011 1111
	//           xx 00xx x0x      
        //  sc1o_src_sc2in=  0010 0000
	//  shift 5 to match bits
	data16 = data16 & 0xF3BF;
	data16 = data16 | (src << 5);
	if( (s = msp34x5g_writeDsp(pC, msp_dsreg_acbreg, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_scart1out_SelectSource, msp34x5g_writeDsp(msp_dsreg_acbreg, data=0x%x) failed %d\n", data16, s));
		goto msp34x5g_scart1out_SelectSource_error;
	}
	
	return RM_OK;
	
msp34x5g_scart1out_SelectSource_error:
	return RM_ERROR;
}



//
// GPIO
//---------------------------------------------------------
RMstatus msp34x5g_SetD_CTR_IO(MSP34X5G_CONFIG *pC, RMuint16 uMask, RMuint16 uData)
{
	RMuint16 data16;
	RMstatus s;

	assert( pC != NULL);

	if( (s = msp34x5g_readDsp(pC, msp_dsreg_acbreg, &data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_SetD_CTR_IO(), msp34x5g_readDsp(msp_dsreg_acbreg) failed %d\n", s));
		return RM_ERROR;
	}
	
	data16 = ((~(uMask << 14)) & data16) | ((uMask << 14) & (uData << 14));
	
	if( (s = msp34x5g_writeDsp(pC, msp_dsreg_acbreg, data16)) != RM_OK )
	{
		DPRINT(("msp34x5g_SetD_CTR_IO(), msp34x5g_writeDsp(msp_dsreg_acbreg, data=0x%x) failed %d\n", data16, s));
		return RM_ERROR;
	}
	
	return RM_OK;	
}



/*
//
// Output: I2S OUT
//-------------------------------------------------------------------------------
RMstatus msp34x5g_i2sout_Configure(MSP34X5G_CONFIG *pC, RMuint16 cfg, RMuint16 cMask)
{
	RMuint16 data16;
	
	//------------------
	// 15 - 0
	// 14:12 - standard detection
	// not modify = 0x7???
	//------------------
	// 11:8 - must be 0
	// 0x70??
	//------------------
	// 7:4 - I2s Configuration
	// 0x70F? - 
	//------------------
	// 3 - digio
	// 2 - must be 0
	// 1 - digio
	// 0 - sound selection
	// not modify = 0x70FB
	RMuint16 mask = 0x70FB;
	
	assert( (cMask & (~(MSP34X5G_I2SOUT_PIN_MASK | MSP34X5G_I2SOUT_MODE_MASK | 
			    MSP34X5G_I2SOUT_STROBEWS_MASK | MSP34X5G_I2SOUT_BIT_MASK))) == 0 );
	
	
	if( msp34x5g_readDemod(pC, msp_dmreg_modus, &data16) != RM_OK )
	{
		DPRINT(("msp34x5g_i2sout_configure() readDemod(modus) failed\n"));
		return RM_ERROR;
	}
	// Read from Demodulator is only valid at designated registers?!  read from modus will always return 0
	// Read from Dsp works however...
	DPRINT(("msp34x5g_readDemod(modus) = 0x%x\n", data16));

	// bit mask is on a different register
	mask = mask & (~(cMask & (~MSP34X5G_I2SOUT_BIT_MASK)));	
	// zero out the changing bits
	data16 = data16 & mask;
	// put in the new configuration
	data16 = data16 | (cfg & (cMask & (~MSP34X5G_I2SOUT_BIT_MASK)));
			
	if( msp34x5g_writeDemod(pC, msp_dmreg_modus, data16) != RM_OK )
	{
		DPRINT(("msp34x5g_i2sout_configure() writeDemod(modus, 0x%x) failed\n", data16));
		return RM_ERROR;
	}
	DPRINT(("msp34x5g_writeDemod(modus, 0x%x)\n", data16));
	
	if( cMask & MSP34X5G_I2SOUT_BIT_MASK )
	{
		if( cfg & MSP34X5G_I2SOUT_BIT_32 )
			data16 = 0x0001;
		else
			data16 = 0x0000;

		if( msp34x5g_writeDemod(pC, msp_dmreg_i2sconfig, data16) != RM_OK )
		{
			DPRINT(("msp34x5g_i2sout_configure() writeDemod(i2sconfig, 0x%x) failed\n", data16));
			return RM_ERROR;
		}
	}
	
	return RM_OK;
}*/