msp34x5g.c

sigma_designs的tuner驱动

/**********************************************************************
 * msp34x5g.c
 * msp34x5g api implementation
 *
 * Copyright (C) 2004 Sigma Designs, Inc.
 *
 * $Log: msp34x5g.c,v $
 * Revision 1.2  2006/01/22 00:32:26  bertrand
 * Ported contents of set_tron from dcc_2_branch to HEAD
 *
 * Revision 1.1.1.1.2.2  2005/06/23 11:23:15  michon
 * fixbuild
 *
 * Revision 1.1.1.1  2005/03/10 00:06:00  bertrand
 * Initial import of the DTV specific code into the ndc repository
 *
 * Revision 1.1.1.1  2004/11/10 03:02:41  jpong
 * i2c devices
 *
 * Revision 1.14  2004/10/29 04:21:40  jpong
 * dk modes, fm prescale IMPORTANT change
 *
 * Revision 1.13  2004/09/03 01:31:02  jpong
 * GPIO still need to add in test.c, not added
 *
 * Revision 1.11  2004/07/15 02:23:00  jpong
 * changed names due to scart1 (out)  and scart dsp (in)
 *
 * Revision 1.9  2004/07/02 00:13:16  jpong
 * read Demod (modus) always returns zero
 * so you have to set everything in the beginning
 * read Dsp (anything) seems to be ok though.
 *
 * implemented specific board configurations, not tested
 * still need to implement interactive mode for the updated api in the test program
 *
 *
 **********************************************************************/
#include <stdio.h>
 
//Standard 86xx includes
#define ALLOW_OS_CODE 1
#include "rmdef/rmdef.h"
#include "llad/include/gbus.h"
#include "emhwlib_hal/include/emhwlib_registers.h"

//86xx i2c
#include "emhwlib_hal/i2c/include/i2c_hal.h"

//helper includes
#include "../helper/helper.h"
#include "../emi2c/emi2c.h"

//msp34x5g includes
#include "msp34x5g.h"

RMstatus msp_i2c_write(EMI2C_CONFIG *pC, RMuint8 *pData, RMuint32 size);
RMstatus msp_i2c_read(EMI2C_CONFIG *pC, RMuint8 rdAddr, RMuint16 *pData16);
RMvoid translate_i2c_to_emi2c(struct i2c* pi2c, EMI2C_CONFIG *pemi2c);

//
//
// LOW LEVEL INTERNALS
//-------------------------------------------------------------------------------------------
// we need emi2c because the default is not 100% i2c compliant.
EMI2C_CONFIG msp_i2c = {
	NULL, 	// gbus
	REG_BASE_system_block,
	0, 1, 	// pio
	
	0, 	// additional delay
	1000,	// SclHiTimeout, msp34x5g will hold the scl line
	0	// no flags
};

// internal helpers
RMvoid translate_i2c_to_emi2c(struct i2c* pi2c, EMI2C_CONFIG *pemi2c)
{
	pemi2c->pGBus = pi2c->pGBus;
	pemi2c->PIO_Clock = pi2c->PioClock;
	pemi2c->PIO_Data = pi2c->PioData;
	pemi2c->RegBase = pi2c->RegBase;
	
	assert( pi2c->RegBase == REG_BASE_system_block );
}

RMstatus msp_i2c_write(EMI2C_CONFIG *pC, RMuint8 *pData, RMuint32 size)
{
	RMstatus s;
	RMuint32 i;
	RMuint8 nack;
	
	assert( size != 0 );
	assert( pData != NULL );
	assert( pC != NULL );

	if( (s = emi2c_start(pC)) != RM_OK )
		return s;
	for( i = 0; i < size; i++)
	{
		if( (s = emi2c_sendbyte(pC, pData[i], &nack)) != RM_OK )
		{
			emi2c_stop(pC);
			return s;
		}
		if( nack != 0 )
			return RM_ERROR;
	}
	return RM_OK;
}

RMstatus msp_i2c_read(EMI2C_CONFIG *pC, RMuint8 rdAddr, RMuint16 *pData16)
{
	RMstatus s;
	RMuint8 nack;
	RMuint8 buffer[2];
	
	assert(pC != NULL);
	assert(pData16 != NULL);
	
	if( (s = emi2c_start(pC)) != RM_OK )
		return s;
	if( (s = emi2c_sendbyte(pC, rdAddr, &nack)) != RM_OK )
	{
		emi2c_stop(pC);
		return s;
	}
	if( nack != 0 )
		return RM_ERROR;
	// high byte
	if( (s = emi2c_readbyte(pC, buffer+1, 0)) != RM_OK )
	{
		emi2c_stop(pC);
		return s;
	}
	//lowbyte
	if( (s = emi2c_readbyte(pC, buffer, EMI2C_SEND_NACK)) != RM_OK )
	{
		emi2c_stop(pC);
		return s;
	}
	s = emi2c_stop(pC);
	
	*pData16 = buffer[0] + (buffer[1] << 8);	
	return s;
}

//
// Manual Register Control
//----------------------------------------------------
RMstatus msp34x5g_writeReg(MSP34X5G_CONFIG* pC, RMuint8 subAddr, RMuint16 regAddr, RMuint16 data)
{
	RMstatus s;
	RMuint8 buffer[6];

	assert( pC != NULL);
	translate_i2c_to_emi2c(&(pC->i2cConfig), &msp_i2c);
	
	buffer[0] = (pC->i2cConfig).WrAddr;
	buffer[1] = subAddr;
	buffer[2] = (regAddr & 0xFF00) >> 8;
	buffer[3] = regAddr & 0xFF;
	buffer[4] = (data & 0xFF00) >> 8;
	buffer[5] = data & 0xFF;
	
	if( (s = msp_i2c_write(&msp_i2c, buffer, 6)) != RM_OK )
	{
		emi2c_stop(&msp_i2c);
		return s;
	}
		
	return emi2c_stop(&msp_i2c);
	//return I2C_Write(&(pC->i2cConfig), subAddr, buffer, 4);
}


RMstatus msp34x5g_readReg(MSP34X5G_CONFIG* pC, RMuint8 subAddr, RMuint16 regAddr, RMuint16* pData)
{
	RMuint8 buffer[4];
	RMstatus s;
	//RMuint8 nack;

	assert( pC != NULL);
	assert( pData != NULL);
	translate_i2c_to_emi2c(&(pC->i2cConfig), &msp_i2c);

	buffer[0] = (pC->i2cConfig).WrAddr;
	buffer[1] = subAddr;
	buffer[2] = (regAddr & 0xFF00) >> 8;
	buffer[3] = regAddr & 0xFF;

	
	if( (s = msp_i2c_write(&msp_i2c, buffer, 4)) != RM_OK )
	{
		emi2c_stop(&msp_i2c);
		return s;
	}	
	// restart, NO STOP
	return msp_i2c_read(&msp_i2c, (pC->i2cConfig).RdAddr, pData); // has stop inside;

	//I2C_Write(&(pC->i2cConfig), subAddr, buffer, 2);
	//I2C_Read_NoSubAddr(&(pC->i2cConfig), buffer, 2);
	
	//*pData = (buffer[0] << 8) | buffer[1];

	//return RM_OK;
}


RMstatus msp34x5g_write(MSP34X5G_CONFIG *pC, RMuint8 subAddr, RMuint16 data)
{
	RMuint8 buffer[4];
	RMstatus s;
	//RMuint8 nack;
	
	assert( pC != NULL);
	translate_i2c_to_emi2c(&(pC->i2cConfig), &msp_i2c);

	buffer[0] = (pC->i2cConfig).WrAddr;
	buffer[1] = subAddr;
	buffer[2] = (data & 0xFF00) >> 8;
	buffer[3] = data & 0xFF;

	if( (s = msp_i2c_write(&msp_i2c, buffer, 4)) != RM_OK )
	{
		emi2c_stop(&msp_i2c);
		return s;
	}
	return emi2c_stop(&msp_i2c);
	//return I2C_Write_NoSubAddr(&(pC->i2cConfig), buffer, 3);
}


RMstatus msp34x5g_read(MSP34X5G_CONFIG *pC, RMuint8 subAddr,  RMuint16 *pData)
{
	RMuint8 buffer[2];
	RMstatus s;
	//RMuint8 nack;
	
	assert( pC != NULL);
	assert( pData != NULL);
	translate_i2c_to_emi2c(&(pC->i2cConfig), &msp_i2c);
	
	//I2C_Read(&(pC->i2cConfig), subAddr, buffer, 2);
	//pData = (buffer[0] << 8) | buffer[1];

	buffer[0] = (pC->i2cConfig).WrAddr;
	buffer[1] = subAddr;
	
	if( (s = msp_i2c_write(&msp_i2c, buffer, 2)) != RM_OK )
	{
		emi2c_stop(&msp_i2c);
		return s;
	}	
	// restart, NO STOP
	return msp_i2c_read(&msp_i2c, (pC->i2cConfig).RdAddr, pData); // has stop inside;
	
}


//
// High Level Interfaces
//-------------------------------------------------------------------------------
RMstatus msp34x5g_detect(MSP34X5G_CONFIG *pC)
{
	RMstatus s;
	RMuint16 Data16;
	
	if( msp34x5g_readDsp(pC, 0x001E, &Data16) != RM_OK )
		return RM_NOT_FOUND;
		
	if( Data16 != 0x0207 )
		return RM_NOT_FOUND;
		
	s = msp34x5g_readDsp(pC, 0x001F, &Data16);
	DPRINT(("msp34x5g_detect() [Product/8 RomVer/8] = 0x%.4x\n  ", Data16));
	return s;
}


RMstatus msp34x5g_reset(MSP34X5G_CONFIG *pC)
{
	if( msp34x5g_writeControl(pC, 0x8000) != RM_OK )
		return RM_ERROR;
		
	return msp34x5g_writeControl(pC, 0x0000);
}



//
//Input: Demodulator Block
//-------------------------------------------------------------------------------
RMstatus msp34x5g_demod_init(MSP34X5G_CONFIG *pC,  MSP34X5G_DETECT_45MHZ nD45mhz, MSP34X5G_DETECT_65MHZ nD65mhz, MSP34X5G_DIGIO_MODE digIOMode, RMuint16 i2sMode)
{
	RMuint16 data16;

	
	// [0] = 1, automatic sound select ON
	data16 = 0x0001;
	
	// [15] = 0
	// [14:13] 4.5 mhz carrier
	switch( nD45mhz )
	{
	case msp_45mhz_MKorea:
		break;
	case msp_45mhz_MBtsc:
		data16 = data16 | (0x01 << 13);
		break;
	case msp_45mhz_MJapan:
		data16 = data16 | (0x02 << 13);
		break;
	case msp_45mhz_ChromaCarrier:
		data16 = data16 | (0x03 << 13);
		break;
	
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	
	// [12] 6.5Mhz carrier
	switch( nD65mhz )
	{
	case msp_65mhz_LSecam:
		break;
	case msp_65mhz_DK123Nicam:
		data16 = data16 | (0x01 << 12);
		break;
		
	default:
		return RM_INVALID_PARAMETER;
		break;
	}
	
	/*
	typedef enum {msp_demod_btsc=0x01} MSP34X5G_DEMOD_MODE;

	if( demodMode == msp_demod_btsc )
	{
		// <2>
		if( msp34x5g_writeDsp(pC, msp_dsreg_fm_premat, 0x2402) != RM_OK) //FM prescale, btsc stereo
		{
			DPRINT(("msp34x5g_init() writeDsp(fm_premat) failed\n"));
			return RM_ERROR;
		}

		// [14:12] = 0x2    0 01(4.5mhz=btsc) 0(6.5mhz=SECAM)
		// [0] = 1          1(Automatic Sound Sel)
		data16 = 0x2001;
	}
	else
		return RM_INVALID_PARAMETER;
	*/
	
	switch( digIOMode )
	{
	case msp_digio_outputenable:
		// [3] = 0;
		break;
	
	case msp_digio_tristate:
		data16 = data16 | 0x0008;
		break;
			
	case msp_digio_out_and_interrupt:
		// [3] = 0;
		// [1] = 1;
		data16 = data16 | 0x0002;
		break;
		
	default:
		DPRINT(("msp34x5g_init() digIOMode %d invalid\n", digIOMode));
		return RM_INVALID_PARAMETER;
		break;
	}
	
	// no extra options...
	assert( (i2sMode & ~(MSP34X5G_I2SOUT_PIN_TRISTATE | MSP34X5G_I2SOUT_MODE_SLAVE | MSP34X5G_I2SOUT_STROBEWS_1CLK | MSP34X5G_I2SOUT_BIT_32)) == 0 );
	// zero out lsb, it is taken care of in another register.
	data16 = data16 | (i2sMode & (~MSP34X5G_I2SOUT_BIT_32));
	
	// <1> (typcal configuration, not below)
	// 0 01(4.5mhz=btsc) 0(6.5mhz=SECAM) 0000 0(AUD_CL_OUT=X) 0(I2S STRBalign) 0(I2S master) 0(I2S=X) 
	// 0(Dig IO=active for Test Point) 0 1(DigIO Status) 1(Automatic Sound Sel)
	// = 0x2003
	if( msp34x5g_writeDemod(pC, msp_dmreg_modus, data16) != RM_OK )
	{
		DPRINT(("msp34x5g_init() writeDemod(modus) failed\n"));
		return RM_ERROR;
	}
	
	if( i2sMode & MSP34X5G_I2SOUT_BIT_32 )
		data16 = 0x0001;
	else
		data16 = 0x0000;
	if( msp34x5g_writeDemod(pC, msp_dmreg_i2sconfig, data16) != RM_OK )
	{
		DPRINT(("msp34x5g_i2sout_configure() writeDemod(i2sconfig, 0x%x) failed\n", data16));
		return RM_ERROR;
	}
	
	return RM_OK;
}


RMstatus msp34x5g_demod_getDetectedStandard(MSP34X5G_CONFIG* pC, RMuint16 *p)
{
	assert( pC != NULL );
	assert( p != NULL );	

	if( msp34x5g_readDemod(pC, msp_dmreg_standardresult, p) != RM_OK )
		return RM_ERROR;
	
	return RM_OK;
}