msp34x5g.h

sigma_designs的tuner驱动

/**********************************************************************
 * msp34x5g.h
 * msp34x5g api header
 *
 * Copyright (C) 2004 Sigma Designs, Inc.
 *
 * $Log: msp34x5g.h,v $
 * Revision 1.1.1.1  2005/03/10 00:06:00  bertrand
 * Initial import of the DTV specific code into the ndc repository
 *
 * Revision 1.2  2004/11/18 00:58:35  jpong
 * i2s word strobe frequency is 32kHZ
 *
 * Revision 1.1.1.1  2004/11/10 03:02:41  jpong
 * i2c devices
 *
 * Revision 1.13  2004/10/29 04:21:40  jpong
 * dk modes, fm prescale IMPORTANT change
 *
 * Revision 1.12  2004/09/03 01:30:23  jpong
 * added D_CTR_IO_X functionality (GPIO)
 *
 * Revision 1.11  2004/07/15 02:23:00  jpong
 * changed names due to scart1 (out)  and scart dsp (in)
 *
 * Revision 1.9  2004/07/08 01:15:50  jpong
 * define error for header prototype fix
 *
 * Revision 1.8  2004/07/07 02:56:41  jpong
 * put in interactive mode for new demod init
 * still need sample to poll/interrupt for SAP
 *
 * Revision 1.7  2004/07/02 00:13:16  jpong
 * read Demod (modus) always returns zero
 * so you have to set everything in the beginning
 * read Dsp (anything) seems to be ok though.
 *
 * implemented specific board configurations, not tested
 * still need to implement interactive mode for the updated api in the test program
 *
 *
 **********************************************************************/
 
 #define MSP34X5G_I2C_ADDR		0x80
typedef struct tagMSP34X5G_CONFIG {
	struct i2c i2cConfig;
} MSP34X5G_CONFIG;


// Manual Register Control
//-----------------------------------------------------------------------------
#define MSP34X5G_SADDR_WRDEMOD		0x10
#define	MSP34X5G_SADDR_RDDEMOD		0x11
#define MSP34X5G_SADDR_WRDSP		0x12
#define	MSP34X5G_SADDR_RDDSP		0x13
RMstatus msp34x5g_writeReg(MSP34X5G_CONFIG* pC, RMuint8 subAddr, RMuint16 regAddr, RMuint16 data);
RMstatus msp34x5g_readReg(MSP34X5G_CONFIG* pC, RMuint8 subAddr, RMuint16 regAddr, RMuint16* pData);

#define MSP34X5G_SADDR_CONTROL		0x00
RMstatus msp34x5g_write(MSP34X5G_CONFIG *pC, RMuint8 subAddr, RMuint16 data);
RMstatus msp34x5g_read(MSP34X5G_CONFIG *pC, RMuint8 subAddr, RMuint16 *pData);


static inline RMstatus msp34x5g_readControl(MSP34X5G_CONFIG *pC, RMuint16 *pData)
{
	return msp34x5g_read(pC, MSP34X5G_SADDR_CONTROL, pData);
}

static inline RMstatus msp34x5g_writeControl(MSP34X5G_CONFIG *pC, RMuint16 data)
{
	return msp34x5g_write(pC, MSP34X5G_SADDR_CONTROL, data);
}

typedef enum { 
msp_dsreg_fm_premat=0x000E, msp_dsreg_scart1_srcmat=0x000A, msp_dsreg_acbreg=0x0013,
msp_dsreg_vol_scart1=0x0007, msp_dsreg_scartdsp_prescale=0x000D
} MSP34X5G_DSP_REGISTER;
static inline RMstatus msp34x5g_readDsp(MSP34X5G_CONFIG *pC, RMuint16 regAddr, RMuint16 *pData)
{
	return msp34x5g_readReg(pC, MSP34X5G_SADDR_RDDSP, regAddr, pData);
}

static inline RMstatus msp34x5g_writeDsp(MSP34X5G_CONFIG *pC, RMuint16 regAddr, RMuint16 data)
{
	return msp34x5g_writeReg(pC, MSP34X5G_SADDR_WRDSP, regAddr, data);
}

typedef enum { 
msp_dmreg_standardselect=0x0020, msp_dmreg_modus=0x0030, msp_dmreg_i2sconfig=0x0040,
msp_dmreg_standardresult=0x007E, msp_dmreg_status = 0x0200 } MSP34X5G_DEMOD_REGISTER;
static inline RMstatus msp34x5g_readDemod(MSP34X5G_CONFIG *pC, MSP34X5G_DEMOD_REGISTER regAddr, RMuint16 *pData)
{
	return msp34x5g_readReg(pC, MSP34X5G_SADDR_RDDEMOD, regAddr, pData);
}

static inline RMstatus msp34x5g_writeDemod(MSP34X5G_CONFIG *pC, MSP34X5G_DEMOD_REGISTER regAddr, RMuint16 data)
{
	return msp34x5g_writeReg(pC, MSP34X5G_SADDR_WRDEMOD, regAddr, data);
}




//Block Diagram
//--------------------------------------------------------------------------------
//
//
//   Inputs                                      Matrices                 Outputs
//   VVVVVV                                      VVVVVVVV                 VVVVVVV
//
//               Demodulator (0,1,3,4)
//   ANA_IN1+----FM/AM, StA/B, St&A, St&B-----|
//                                            |--Loudspeaker[Not Impl.]---DACM OUT
//   I2S1(5) [Not Impl.]----------------------|
//                                            |--I2S----------------------I2S_OUT
//   I2S2(6) [Not Impl.]----------------------|
//                                            |--Quasi Peak[Not Impl.]
//               SCART1_DSP (2) --------------|--SCART1 DA----------|
//                |                                                 |-----SCART1OUT
//   SC1_IN  -----|-------------------------------------------------|
//   SC2_IN  -----|-------------------------------------------------|
//   MONO_IN -----|-------------------------------------------------|
//
//
//   OTHER
//   D_CTR_IO_0 ------
//   D_CTR_IO_1 ------
//
//   NOTE****  THE I2S Word Strobe Frequency is 32kHZ
//


//Control
//-------------------------------------------------------------------------------
RMstatus msp34x5g_reset(MSP34X5G_CONFIG *pC);
RMstatus msp34x5g_detect(MSP34X5G_CONFIG *pC);


//Input: Demodulator Block
//Output: I2S
//-------------------------------------------------------------------------------
#define MSP34X5G_I2SOUT_PIN_ACTIVE		0x0000
// Active also changes AUD_CL_OUT to output, vice versa for tristate
#define MSP34X5G_I2SOUT_PIN_TRISTATE		0x0090  // basically i2s OFF
#define MSP34X5G_I2SOUT_MODE_MASTER		0x0000
#define MSP34X5G_I2SOUT_MODE_SLAVE		0x0020
#define MSP34X5G_I2SOUT_STROBEWS_BOUND		0x0000
#define MSP34X5G_I2SOUT_STROBEWS_1CLK		0x0040
#define MSP34X5G_I2SOUT_BIT_16			0x0000
#define MSP34X5G_I2SOUT_BIT_32			0x0001
typedef enum {msp_digio_tristate=0x01, msp_digio_outputenable, msp_digio_out_and_interrupt} MSP34X5G_DIGIO_MODE;
 // btsc, Prescale set to 100 khZ FM deviation
typedef enum { msp_45mhz_MKorea=MSP34X5G_ENUM+0x100, msp_45mhz_MBtsc, msp_45mhz_MJapan, msp_45mhz_ChromaCarrier } MSP34X5G_DETECT_45MHZ;
typedef enum { msp_65mhz_LSecam=MSP34X5G_ENUM+0x200, msp_65mhz_DK123Nicam} MSP34X5G_DETECT_65MHZ;
RMstatus msp34x5g_demod_init(MSP34X5G_CONFIG *pC,  MSP34X5G_DETECT_45MHZ nD45mhz, MSP34X5G_DETECT_65MHZ nD65mhz, MSP34X5G_DIGIO_MODE digIOMode, RMuint16 i2sMode);

typedef enum { 	msp_fm28khz=MSP34X5G_ENUM+0x300, msp_fm50khz, msp_fm75khz, msp_fm100khz, msp_fm150khz, msp_fm180khz,
		msp_fm_hdev2_150khz, msp_fm_hdev2_360khz, msp_fm_hdev3_450khz, msp_fm_hdev3_540khz,
		msp_fm_satellite, msp_am } MSP34X5G_FMamPRESCALE;
RMstatus msp34x5g_demod_InputFMamPrescale(MSP34X5G_CONFIG* pC, MSP34X5G_FMamPRESCALE p);

//Input: Demodulator Block 
//-------------------------------------------------------------------------------
RMstatus msp34x5g_demod_getDetectedStandard(MSP34X5G_CONFIG* pC, RMuint16 *p);

#define MSP_IS_PRIMARY_CARRIER(x)	((x & 0x02)?0:1)
#define MSP_IS_SECOND_CARRIER(x)	((x & 0x04)?0:1)
#define MSP_DIGIO_0(x)			((x & 0x08)?1:0)
#define MSP_DIGIO_1(x)			((x & 0x10)?1:0)

#define MSP_STEREO_OR_MONO(x)		((x & 0x40)?1:0) //0 = mono
#define MSP_NICAM_MONO(x)		((x & 0x80)?1:0)
#define MSP_SAP_AVAILABLE(x)		((x & 0x100)?1:0)
#define MSP_ANALOG_SOUND(x)		( ((x & 0x20) || (x & 0x200))?0:1 )   //[5,9] = 00
#define MSP_NICAM_SOUND(x)		( ((x & 0x20) && ((x & 0x200)?0:1))?1:0 ) //[5,9] = 10
#define MSP_NICAM_BAD(x)		( ((x & 0x20) && (x & 0x200))?1:0 )  //[5,9] = 11
RMstatus msp34x5g_demod_getStatus(MSP34X5G_CONFIG *pC, RMuint16 *p);

typedef enum {	msp_standard_autodetect=0x0001, msp_standard_btscstereo=0x0020, msp_standard_btscmonosap=0x0021, 
		msp_standard_dk1stereo=0x0004, msp_standard_dk2stereo=0x0005, msp_standard_dk3stereo=0x0007, msp_standard_dknicam=0x000b,
		msp_standard_dkmono_hdev3=0x0006, msp_standard_dknicam_hdev2=0x000c, msp_standard_dknicam_hdev3=0x000d} 
MSP34X5G_STANDARD;
RMstatus msp34x5g_demod_selectStandard(MSP34X5G_CONFIG* pC, MSP34X5G_STANDARD s);


//Input: SCART1 DSP
//-------------------------------------------------------------------------------
typedef enum{sc_dsp_src_sc1in=0x00, sc_dsp_src_monoin=0x08, sc_dsp_src_sc2in=0x10, sc_dsp_mute=0x19}
MSP34X5G_SC_DSP_SRC;
RMstatus msp34x5g_scartdsp_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_SC_DSP_SRC src);
#define MSPSCARTDSP_PRESCALE_OFF	0x00
#define MSPSCARTDSP_PRESCALE_0DB	0x19
#define MSPSCARTDSP_PRESCALE_14DB	0x7f
RMstatus msp34x5g_scartdsp_InputPrescale(MSP34X5G_CONFIG *pC, RMuint8 db);

//MATRIX Operations
//-------------------------------------------------------------------------------
typedef enum{matrix_main=0x0008, matrix_sc1DA=0x000a, matrix_i2s=0x000b, matrix_qpeak=0x000c}
MSP34X5G_MATRIX;

typedef enum{	matrix_src_demodFMAM=0x00, matrix_src_stereoAB=0x01, matrix_src_stereoA=0x03, matrix_src_stereoB=0x04,
		matrix_src_SCARTin=0x02, matrix_src_I2S1=0x05, matrix_src_I2S2=0x06}
MSP34X5G_MATRIX_SRC;
RMstatus msp34x5g_matrix_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_MATRIX m, MSP34X5G_MATRIX_SRC src);

typedef enum {
matrix_mode_soundAMono=0x00, matrix_mode_soundBMono=0x10, matrix_mode_stereo=0x20, matrix_mode_mono=0x30, matrix_mode_sumDiff=0x40,
matrix_mode_abXchange=0x50, matrix_mode_phaseChangeB=0x60, matrix_mode_phaseChangeA=0x70, matrix_mode_onlyA=0x80, matrix_mode_onlyB=0x90
} MSP34X5G_MATRIX_MODE;
RMstatus msp34x5g_matrix_SelectMode(MSP34X5G_CONFIG *pC, MSP34X5G_MATRIX m, MSP34X5G_MATRIX_MODE md);


//Output: SCART1 OUT
//-------------------------------------------------------------------------------
#define MSPVOL_MAX	0x7F	//+12db
#define MSPVOL_0DB	0x73	// 0db
#define MSPVOL_MID	0x3F
#define MSPVOL_MIN	0x01	// -114db
#define MSPVOL_MUTE	0x00	// mute
RMstatus msp34x5g_scart1out_SetVolume(MSP34X5G_CONFIG *pC, RMuint8 db);

typedef enum {sc1out_src_sc2in = 0x20, sc1out_src_monoin=0x40, sc1out_src_sc1DA=0x60, sc1out_src_sc1in=0x22, sc1out_mute=0x62 } 
MSP34X5G_SC1OUT_SRC;
// 8610 HDTV Reference design inputs = sc1o_src_monoin, sc1o_src_sc1DA, sc1o_mute
// 8620L Reference Design  = output only a TP, not used, set to mute unless under test.
RMstatus msp34x5g_scart1out_SelectSource(MSP34X5G_CONFIG *pC, MSP34X5G_SC1OUT_SRC src);


// GPIO
//---------------------------------------------------------
// D_CTR_IO configuration msp34x5g_demod_init()
// D_CTR_IO get msp34x5g_demod_getStatus()
// bit 0 = D_CTR_IO_0
// bit 1 = D_CTR_IO_1
// use the mask so that you don't change the bit you don't want to
RMstatus msp34x5g_SetD_CTR_IO(MSP34X5G_CONFIG *pC, RMuint16 uMask, RMuint16 uData);


//Output: I2S OUT
//-------------------------------------------------------------------------------
//RMstatus msp34x5g_i2sout_Configure(MSP34X5G_CONFIG *pC, RMuint16 cfg, RMuint16 cMask);