📄 at91.lst
字号:
##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.42A/W32 EVALUATION 09/Sep/2008 07:54:46 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = E:\AT91EBxx\at91.c #
# Command line = E:\AT91EBxx\at91.c --fpu None -D RAMCODE=1 -lCN #
# E:\AT91EBxx\ramcode-EBxx\List\ -o #
# E:\AT91EBxx\ramcode-EBxx\Obj\ -z3 --no_cse #
# --no_unroll --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --cpu_mode #
# arm --endian little --cpu ARM7TDMI --stack_align 4 #
# --interwork -e --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Evaluation\arm\LIB\dl4tpainl8n.h" -I "C:\Program #
# Files\IAR Systems\Embedded Workbench 4.0 #
# Evaluation\arm\INC\" #
# List file = E:\AT91EBxx\ramcode-EBxx\List\at91.lst #
# Object file = E:\AT91EBxx\ramcode-EBxx\Obj\at91.r79 #
# #
# #
##############################################################################
E:\AT91EBxx\at91.c
1
2 /*
3 * $Revision: 1.8 $
4 */
5
6 #include "config.h"
\ In segment DATA_AN, at 0xffff4004
\ union <unnamed> volatile __data _A___PS_PCER
\ _A___PS_PCER:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff000
\ union <unnamed> volatile __data _A___AIC_SMR0
\ _A___AIC_SMR0:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff008
\ union <unnamed> volatile __data _A___AIC_SMR2
\ _A___AIC_SMR2:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff010
\ union <unnamed> volatile __data _A___AIC_SMR4
\ _A___AIC_SMR4:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff080
\ union <unnamed> volatile __data _A___AIC_SVR0
\ _A___AIC_SVR0:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff088
\ union <unnamed> volatile __data _A___AIC_SVR2
\ _A___AIC_SVR2:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff090
\ union <unnamed> volatile __data _A___AIC_SVR4
\ _A___AIC_SVR4:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff100
\ union <unnamed> volatile __data _A___AIC_IVR
\ _A___AIC_IVR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff120
\ union <unnamed> volatile __data _A___AIC_IECR
\ _A___AIC_IECR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff124
\ union <unnamed> volatile __data _A___AIC_IDCR
\ _A___AIC_IDCR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff128
\ union <unnamed> volatile __data _A___AIC_ICCR
\ _A___AIC_ICCR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff130
\ unsigned long volatile __data __AIC_EOICR
\ __AIC_EOICR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffff134
\ union <unnamed> volatile __data _A___AIC_SPU
\ _A___AIC_SPU:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0000
\ union <unnamed> volatile __data _A___PIO_PER
\ _A___PIO_PER:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0004
\ union <unnamed> volatile __data _A___PIO_PDR
\ _A___PIO_PDR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0010
\ union <unnamed> volatile __data _A___PIO_OER
\ _A___PIO_OER:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0014
\ union <unnamed> volatile __data _A___PIO_ODR
\ _A___PIO_ODR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0030
\ union <unnamed> volatile __data _A___PIO_SODR
\ _A___PIO_SODR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0034
\ union <unnamed> volatile __data _A___PIO_CODR
\ _A___PIO_CODR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff003c
\ union <unnamed> const volatile __data _A___PIO_PDSR
\ _A___PIO_PDSR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xffff0044
\ union <unnamed> volatile __data _A___PIO_IDR
\ _A___PIO_IDR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfff00018
\ union <unnamed> volatile __data _A___SF_PMR
\ _A___SF_PMR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0000
\ union <unnamed> volatile __data _A___US_CR
\ _A___US_CR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0004
\ union <unnamed> volatile __data _A___US_MR
\ _A___US_MR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0008
\ union <unnamed> volatile __data _A___US_IER
\ _A___US_IER:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd000c
\ union <unnamed> volatile __data _A___US_IDR
\ _A___US_IDR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0014
\ union <unnamed> const volatile __data _A___US_CSR
\ _A___US_CSR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0018
\ union <unnamed> const volatile __data _A___US_RHR
\ _A___US_RHR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd001c
\ union <unnamed> volatile __data _A___US_THR
\ _A___US_THR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0020
\ union <unnamed> volatile __data _A___US_BRGR
\ _A___US_BRGR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffd0028
\ union <unnamed> volatile __data _A___US_TTGR
\ _A___US_TTGR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe0000
\ union <unnamed> volatile __data _A___TC_CCR
\ _A___TC_CCR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe0004
\ union <unnamed> volatile __data _A___TC_CMR
\ _A___TC_CMR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe001c
\ union <unnamed> volatile __data _A___TC_RC
\ _A___TC_RC:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe0020
\ union <unnamed> const volatile __data _A___TC_SR
\ _A___TC_SR:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe0024
\ union <unnamed> volatile __data _A___TC_IER
\ _A___TC_IER:
\ 00000000 DS8 4
\ In segment DATA_AN, at 0xfffe0028
\ union <unnamed> volatile __data _A___TC_IDR
\ _A___TC_IDR:
\ 00000000 DS8 4
7
\ In segment DATA_Z, align 4, align-sorted
8 static void(*timer_function)();
\ timer_function:
\ 00000000 DS8 4
\ In segment DATA_Z, align 4, align-sorted
9 static void(*rxrdy_function)();
\ rxrdy_function:
\ 00000000 DS8 4
10
11
12 //
13 // Clock initialization.
14 //
15
16 #if AT91_EB42
17 void AT91_EB42_PllStart()
18 {
19 #define PMC_PLL_LOCK 1 // PLL lock status
20
21 // Speed up the System Frequency to 32 MHz.
22
23 // Stay at PLL B if already set up.
24 if ((__PMC_CGMR & 0x80) == 0)
25 {
26 // Run from 32 kHz until PLL is stabilized.
27 // PLLCOUNT = 197, MUL = 976, CSS = 0, MCKODS = 0, MCKOSS = 1, PLLS = 1, PRES = 0
28 __PMC_CGMR = 0xc503d008;
29
30 // Reading the PMC Status register to detect when the PLL is stabilized
31 while ((__PMC_SR & PMC_PLL_LOCK) != PMC_PLL_LOCK) ;
32 }
33
34 // Commuting from 32 kHz (or other PLL speed) to PLL @ 32 MHz
35 // PLLCOUNT = 197, MUL = 976, CSS = 1, MCKODS = 0, MCKOSS = 1, PLLS = 1, PRES = 0
36 __PMC_CGMR = 0xc503d098;
37
38 // Reading the PMC Status register to detect when the PLL is stabilized
39 while ((__PMC_SR & PMC_PLL_LOCK) != PMC_PLL_LOCK) ;
40
41 // Now the Master clock is the output of PLL @ 32MHz
42 }
43 #endif
44
45 #if AT91_EB55
46 void AT91_EB55_PllStart()
47 {
48 #define APMC_MOSCS 1 // Main oscillator status bit
49 #define APMC_PLL_LOCK 2 // PLL lock status
50
51 int i;
52
53 // Speed up the System Frequency.
54
55 __APMC_CGMR = 0x002F0002; // MOSCEN = 1, OSCOUNT = 47 (1.4ms/30祍)
56
57 // Reading the APMC Status register to detect when the oscillator is stabilized
58 while ((__APMC_SR & APMC_MOSCS) != APMC_MOSCS) ;
59
60 // Commuting from Slow Clock to Main Oscillator (16Mhz)
61 __APMC_CGMR = 0x002F4002; // MOSCEN = 1, OSCOUNT = 47 (1.4ms/30祍)
62
63 // Setup the PLL to 32 MHz clock
64 __APMC_CGMR = 0x032F4102; // MUL = 1, PLLCOUNT = 3, CSS = 1
65
66 // Reading the APMC Status register to detect when the PLL is stabilized
67 // Wait a little extra to ensure stable PLL.
68 for (i = 0; i < 1000; i++)
69 {
70 while ((__APMC_SR & APMC_PLL_LOCK) != APMC_PLL_LOCK) ;
71 }
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -