fmdhal_asm.s

for sdio or sd card source code under pxa270

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; Copyright 2002-2004 Intel Corporation All Rights Reserved.
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   AREA     |.text|, CODE
   ALIGN    4

   EXPORT FMDHAL_ASMInterruptEnable
   EXPORT FMDHAL_ASMInterruptDisable
   

;******************************************************************************
; "FMDHAL_ASMDisableInterrupts"
;
; Description:
;    Disable all interrupts on the Bulverde processor.  We will disable
;    interrupts by setting the FIQ and IRQ disable bits (5 & 6) to 1's in the
;    Current Program Status Register (CPSR). We will save and restore the bit
;    values later.
;
; Processing:
;    Temp      = CPSR
;    ReturnVal = Temp
;    Temp      = Temp | 0xC0
;    CPSR      = Temp
;    return (ReturnVal)
;
; Inputs:
;    None
;
; Return Value:
;    Contents of the CPSR before modified in R0
;
; Register Usage:
;    R12, R0, CPSR
;       R0 contains the return value from this function.  So we restore the
;       values of all the registers except R0 and return gracefully from this
;       function.
;******************************************************************************
FMDHAL_ASMInterruptDisable
FMDDISMASK EQU   0x000000C0        ; AND mask to extract interrupt settings
   STMFD   SP!,  {R12, LR}
   MRS     R12,  CPSR              ; read the current program status register (cpsr) into R12
   MOV     R0,   R12               ; copy R12 into the return value register
   ORR     R12,  R12, #FMDDISMASK  ; set the IRQ and FIQ mask bits to 1.
   LDMIA   SP!,  {R12, PC}         ; Return


;******************************************************************************
; "FMDHAL_ASMEnableInterrupts"
;
; Description:
;    Enable interrupts on the Bulverde processor.  We will re-enable interrupts
;    by restoring the old values that were found in the CPSR when we disabled
;    interrupts.
;
; Processing:
;    Mask = old_CPSR & 0xC0
;    Temp = CPSR
;    Temp = BitClear(Temp, 0xC0)
;    Temp = Temp | Mask
;    CPSR = Temp
;
; Inputs:
;    Old CPSR before interrupts disabled in R0
;
; Return Value:
;    None
;
; Register Usage:
;    R0, R12, CPSR
;******************************************************************************
FMDHAL_ASMInterruptEnable
FMDINTMASK EQU   0x000000C0       ; AND mask to extract interrupt settings
   STMFD   SP!,  {R0-R12, LR}
   AND     R0,   R0, #FMDINTMASK  ; isolate bits 5 and 6, old interrupt settings
   MRS     R12,  CPSR             ; read the current program status register into R12
   BIC     R12,  R12, #FMDINTMASK ; clear bits 5 and 6 in prep for the OR operation
   ORR     R12,  R12, R0          ; OR in the old values that were in bits 5 and 6
   LDMIA   SP!,  {R0-R12, PC}     ; Return



   END