tx3912.h

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#define IODIN_SHIFT     0
#define IODOUT_MASK     0x00007f00
#define IODOUT_SHIFT    8
#define IODIREC_MASK    0x007f0000
#define IODIREC_SHIFT   16
#define IODEBSEL_MASK   0x7f000000
#define IODEBSEL_SHIFT  24

/******************************************************************************
*
*	10  IR module
*
******************************************************************************/

#define IRControl1                  REG_AT(0x0a0)
#define IRControl2                  REG_AT(0x0a4)

/* IR Control 1 Register */
#define IR_CARDRET                  BIT(24)
#define IR_BAUDVAL_MASK             0x00ff0000
#define IR_BAUDVAL_SHIFT            16
#define IR_TESTIR                   BIT(4)
#define IR_DTINVERT                 BIT(3)
#define IR_RXPWR                    BIT(2)
#define IR_ENSTATE                  BIT(1)
#define IR_ENCONSM                  BIT(0)

/* IR Control 2 Register */
#define IR_PER_MASK                 0xff000000
#define IR_PER_SHIFT                24
#define IR_ONTIME_MASK              0x00ff0000
#define IR_ONTIME_SHIFT             16
#define IR_DELAYVAL_MASK            0x0000ff00
#define IR_DELAYVAL_SHIFT           8
#define IR_WAITVAL_MASK             0x000000ff
#define IR_WAITVAL_SHIFT            0

/******************************************************************************
*
*	11  Magicbus Module
*
******************************************************************************/

#define MbusCntrl1		REG_AT(0x0e0)
#define MbusCntrl2		REG_AT(0x0e4)
#define MbusDMACntrl1		REG_AT(0x0e8)
#define MbusDMACntrl2		REG_AT(0x0ec)
#define MbusDMACount		REG_AT(0x0f0)
#define MbusTxReg		REG_AT(0x0f4)
#define MbusRxReg		REG_AT(0x0f8)

#define	MBUS_CLKPOL		BIT(4)
#define	MBUS_SLAVE		BIT(3)
#define	MBUS_FSLAVE		BIT(2)
#define	MBUS_LONG		BIT(1)
#define	MBUS_ENMBUS		BIT(0)

/******************************************************************************
*
*	12  Power module
*
******************************************************************************/

#define PowerControl   	            REG_AT(0x1C4)

#define PWR_ONBUTN                  BIT(31)
#define PWR_PWRINT                  BIT(30)
#define PWR_PWROK                   BIT(29)
#define PWR_VIDRF_MASK              (BIT(28) | BIT(27))
#define PWR_VIDRF_SHIFT             27
#define PWR_SLOWBUS                 BIT(26)
#define PWR_DIVMOD                  BIT(25)
#define PWR_STPTIMERVAL_MASK        (BIT(15) | BIT(14) | BIT(13) | BIT(12))
#define PWR_STPTIMERVAL_SHIFT       12
#define PWR_ENSTPTIMER              BIT(11)
#define PWR_ENFORCESHUTDWN          BIT(10)
#define PWR_FORCESHUTDWN            BIT(9)
#define PWR_FORCESHUTDWNOCC         BIT(8)
#define PWR_SELC2MS                 BIT(7)
#define PWR_BPDBVCC3                BIT(5)
#define PWR_STOPCPU                 BIT(4)
#define PWR_DBNCONBUTN              BIT(3)
#define PWR_COLDSTART               BIT(2)
#define PWR_PWRCS                   BIT(1)
#define PWR_VCCON                   BIT(0)

/******************************************************************************
*
*	13  SIB (Serial Interconnect Bus) Module
*
******************************************************************************/

/* Register locations */
#define SIBSize	      	        REG_AT(0x060)
#define SIBSoundRXStart	      	REG_AT(0x064)
#define SIBSoundTXStart         REG_AT(0x068)
#define SIBTelecomRXStart       REG_AT(0x06C)
#define SIBTelecomTXStart       REG_AT(0x070)
#define SIBControl              REG_AT(0x074)
#define SIBSoundTXRXHolding     REG_AT(0x078)
#define SIBTelecomTXRXHolding   REG_AT(0x07C)
#define SIBSubFrame0Control     REG_AT(0x080)
#define SIBSubFrame1Control     REG_AT(0x084)
#define SIBSubFrame0Status      REG_AT(0x088)
#define SIBSubFrame1Status      REG_AT(0x08C)
#define SIBDMAControl           REG_AT(0x090)

/* SIB Size Register */
#define SIB_SNDSIZE_MASK        0x3ffc0000
#define SIB_SNDSIZE_SHIFT       18
#define SIB_TELSIZE_MASK        0x00003ffc
#define SIB_TELSIZE_SHIFT       2

/* SIB Control Register */
#define SIB_SIBIRQ              BIT(31)
#define SIB_ENCNTTEST           BIT(30)
#define SIB_ENDMATEST           BIT(29)
#define SIB_SNDMONO             BIT(28)
#define SIB_RMONOSNDIN          BIT(27)
#define SIB_SIBSCLKDIV_MASK     (BIT(26) | BIT(25) | BIT(24))
#define SIB_SIBSCLKDIV_SHIFT    24
#define SIB_TEL16               BIT(23)
#define SIB_TELFSDIV_MASK       0x007f0000
#define SIB_TELFSDIV_SHIFT      16
#define SIB_SND16               BIT(15)
#define SIB_SNDFSDIV_MASK       0x00007f00
#define SIB_SNDFSDIV_SHIFT      8
#define SIB_SELTELSF1           BIT(7)
#define SIB_SELSNDSF1           BIT(6)
#define SIB_ENTEL               BIT(5)
#define SIB_ENSND               BIT(4)
#define SIB_SIBLOOP             BIT(3)
#define SIB_ENSF1               BIT(2)
#define SIB_ENSF0               BIT(1)
#define SIB_ENSIB               BIT(0)

/* SIB Frame Format (SIBSubFrame0Status and SIBSubFrame1Status) */
#define SIB_REGISTER_EXT        BIT(31)  /* Must be zero */
#define SIB_ADDRESS_MASK        0x78000000
#define SIB_ADDRESS_SHIFT       27
#define SIB_WRITE               BIT(26)
#define SIB_AUD_VALID           BIT(17)
#define SIB_TEL_VALID           BIT(16)
#define SIB_DATA_MASK           0x00ff
#define SIB_DATA_SHIFT          0

/* SIB DMA Control Register */
#define SIB_SNDBUFF1TIME        BIT(31)
#define SIB_SNDDMALOOP          BIT(30)
#define SIB_SNDDMAPTR_MASK      0x3ffc0000
#define SIB_SNDDMAPTR_SHIFT     18
#define SIB_ENDMARXSND          BIT(17)
#define SIB_ENDMATXSND          BIT(16)
#define SIB_TELBUFF1TIME        BIT(15)
#define SIB_TELDMALOOP          BIT(14)
#define SIB_TELDMAPTR_MASK      0x00003ffc
#define SIB_TELDMAPTR_SHIFT     2
#define SIB_ENDMARXTEL          BIT(1)
#define SIB_ENDMATXTEL          BIT(0)

/******************************************************************************
*
* 	14  SPI module
*
******************************************************************************/

#define SPIControl		REG_AT(0x160)
#define SPITransmit		REG_AT(0x164)
#define SPIReceive		REG_AT(0x164)

#define SPI_SPION		BIT(17)
#define SPI_EMPTY		BIT(16)
#define SPI_DELAYVAL_MASK	(BIT(12) | BIT(13) | BIT(14) | BIT(15))
#define SPI_DELAYVAL_SHIFT	12
#define	SPI_BAUDRATE_MASK	(BIT(8) | BIT(9) | BIT(10) | BIT(11))
#define	SPI_BAUDRATE_SHIFT	8
#define	SPI_PHAPOL		BIT(5)
#define	SPI_CLKPOL		BIT(4)
#define	SPI_WORD		BIT(2)
#define	SPI_LSB			BIT(1)
#define	SPI_ENSPI		BIT(0)

/******************************************************************************
*
*	15  Timer module
*
******************************************************************************/

#define RTChigh	      	REG_AT(0x140)
#define RTClow	        REG_AT(0x144)
#define RTCalarmHigh    REG_AT(0x148)
#define RTCalarmLow     REG_AT(0x14c)
#define RTCtimerControl REG_AT(0x150)
#define RTCperiodTimer  REG_AT(0x154)

/* RTC Timer Control */
#define TIM_FREEZEPRE	BIT(7)
#define TIM_FREEZERTC	BIT(6)
#define TIM_FREEZETIMER	BIT(5)
#define TIM_ENPERTIMER	BIT(4)
#define TIM_RTCCLEAR	BIT(3)

#define	RTC_HIGHMASK	(0xFF)

/* RTC Periodic Timer */
#define	TIM_PERCNT	0xFFFF0000
#define	TIM_PERVAL	0x0000FFFF

/* For a system clock frequency of 36.864MHz, the timer counts at one tick
   every 868nS (ie CLK/32). Therefore 11520 counts gives a 10mS interval
 */
#define PER_TIMER_COUNT (1152000/HZ)

/*
 ***********************************************************************
 *								       *
 * 15  UART Module						       *
 *								       *
 ***********************************************************************
 */
#define TX3912_UARTA_BASE       (REGISTER_BASE + 0x0b0)
#define TX3912_UARTB_BASE       (REGISTER_BASE + 0x0c8)

/*
 * TX3912 UART register offsets
 */
#define TX3912_UART_CTRL1       0x00
#define TX3912_UART_CTRL2       0x04
#define TX3912_UART_DMA_CTRL1   0x08
#define TX3912_UART_DMA_CTRL2   0x0c
#define TX3912_UART_DMA_CNT     0x10
#define TX3912_UART_DATA        0x14

#define UartA_Ctrl1   REG_AT(0x0b0)
#define UartA_Data    REG_AT(0x0c4)

/*
 * Defines for UART Control Register 1
 */
#define TX3912_UART_CTRL1_UARTON	0x80000000
#define UART_TX_EMPTY		BIT(30)
#define UART_PRX_HOLD_FULL	BIT(29)
#define UART_RX_HOLD_FULL	BIT(28)
#define UART_EN_DMA_RX 		BIT(15)
#define UART_EN_DMA_TX 		BIT(14)
#define UART_BREAK_HALT 	BIT(12)
#define UART_DMA_LOOP		BIT(10)
#define UART_PULSE_THREE	BIT(9)
#define UART_PULSE_SIX		BIT(8)
#define UART_DT_INVERT		BIT(7)
#define UART_DIS_TXD		BIT(6)
#define UART_LOOPBACK		BIT(4)
#define TX3912_UART_CTRL1_ENUART	0x00000001
		 
#define SER_SEVEN_BIT		BIT(3)
#define SER_EIGHT_BIT		    0
#define SER_EVEN_PARITY 	(BIT(2) | BIT(1))
#define SER_ODD_PARITY  	BIT(1)
#define SER_NO_PARITY		    0
#define SER_TWO_STOP		BIT(5)
#define SER_ONE_STOP		    0

/*
 * Defines for UART Control Register 2
 *
 *              3.6864MHz
 * divisors =  ----------- - 1
 *             (baud * 16)
 */
#define TX3912_UART_CTRL2_B230400	0x000	/*   0 */
#define TX3912_UART_CTRL2_B115200	0x001	/*   1 */
#define TX3912_UART_CTRL2_B76800	0x002	/*   2 */
#define TX3912_UART_CTRL2_B57600	0x003	/*   3 */
#define TX3912_UART_CTRL2_B38400	0x005	/*   5 */
#define TX3912_UART_CTRL2_B19200	0x00b	/*  11 */
#define TX3912_UART_CTRL2_B9600		0x016	/*  22 */
#define TX3912_UART_CTRL2_B4800		0x02f	/*  47 */
#define TX3912_UART_CTRL2_B2400		0x05f	/*  95 */
#define TX3912_UART_CTRL2_B1200		0x0bf	/* 191 */
#define TX3912_UART_CTRL2_B600		0x17f	/* 383 */
#define TX3912_UART_CTRL2_B300		0x2ff	/* 767 */

#endif	/* __TX3912_H__ */