au1000.h
来自「this SRC packet is the headfiles that MI」· C头文件 代码 · 共 636 行 · 第 1/2 页
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636 行
#define PC0_TRIM (PC_BASE + 0)#define PC0_COUNTER_WRITE (PC_BASE + 4)#define PC0_MATCH0 (PC_BASE + 8)#define PC0_MATCH1 (PC_BASE + 0xC)#define PC0_MATCH2 (PC_BASE + 0x10)#define PC0_COUNTER_READ (PC_BASE + 0x40)/* Programmable Counter 1 Registers */#define PC1_TRIM (PC_BASE + 0x44)#define PC1_COUNTER_WRITE (PC_BASE + 0x48)#define PC1_MATCH0 (PC_BASE + 0x4C)#define PC1_MATCH1 (PC_BASE + 0x50)#define PC1_MATCH2 (PC_BASE + 0x54)#define PC1_COUNTER_READ (PC_BASE + 0x58)/* I2S Controller */#define I2S_DATA 0x11000000#define I2S_CONFIG_STATUS 0x11000001#define I2S_CONTROL 0x11000002/* Ethernet Controllers */#define AU1000_ETH0_BASE 0x10500000#define AU1000_ETH1_BASE 0x10510000/* 4 byte offsets from AU1000_ETH_BASE */#define MAC_CONTROL 0x0 #define MAC_RX_ENABLE (1<<2) #define MAC_TX_ENABLE (1<<3) #define MAC_DEF_CHECK (1<<5) #define MAC_SET_BL(X) (((X)&0x3)<<6) #define MAC_AUTO_PAD (1<<8) #define MAC_DISABLE_RETRY (1<<10) #define MAC_DISABLE_BCAST (1<<11) #define MAC_LATE_COL (1<<12) #define MAC_HASH_MODE (1<<13) #define MAC_HASH_ONLY (1<<15) #define MAC_PASS_ALL (1<<16) #define MAC_INVERSE_FILTER (1<<17) #define MAC_PROMISCUOUS (1<<18) #define MAC_PASS_ALL_MULTI (1<<19) #define MAC_FULL_DUPLEX (1<<20) #define MAC_NORMAL_MODE 0 #define MAC_INT_LOOPBACK (1<<21) #define MAC_EXT_LOOPBACK (1<<22) #define MAC_DISABLE_RX_OWN (1<<23) #define MAC_BIG_ENDIAN (1<<30) #define MAC_RX_ALL (1<<31)#define MAC_ADDRESS_HIGH 0x4#define MAC_ADDRESS_LOW 0x8#define MAC_MCAST_HIGH 0xC#define MAC_MCAST_LOW 0x10#define MAC_MII_CNTRL 0x14 #define MAC_MII_BUSY (1<<0) #define MAC_MII_READ 0 #define MAC_MII_WRITE (1<<1) #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)#define MAC_MII_DATA 0x18#define MAC_FLOW_CNTRL 0x1C #define MAC_FLOW_CNTRL_BUSY (1<<0) #define MAC_FLOW_CNTRL_ENABLE (1<<1) #define MAC_PASS_CONTROL (1<<2) #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)#define MAC_VLAN1_TAG 0x20#define MAC_VLAN2_TAG 0x24/* Ethernet Controller Enable */#define MAC0_ENABLE 0x10520000#define MAC1_ENABLE 0x10520004 #define MAC_EN_CLOCK_ENABLE (1<<0) #define MAC_EN_RESET0 (1<<1) #define MAC_EN_TOSS (1<<2) #define MAC_EN_CACHEABLE (1<<3) #define MAC_EN_RESET1 (1<<4) #define MAC_EN_RESET2 (1<<5) #define MAC_DMA_RESET (1<<6)/* Ethernet Controller DMA Channels */#define MAC0_TX_DMA_ADDR 0x14004000#define MAC1_TX_DMA_ADDR 0x14004200/* offsets from MAC_TX_RING_ADDR address */#define MAC_TX_BUFF0_STATUS 0x0 #define TX_FRAME_ABORTED (1<<0) #define TX_JAB_TIMEOUT (1<<1) #define TX_NO_CARRIER (1<<2) #define TX_LOSS_CARRIER (1<<3) #define TX_EXC_DEF (1<<4) #define TX_LATE_COLL_ABORT (1<<5) #define TX_EXC_COLL (1<<6) #define TX_UNDERRUN (1<<7) #define TX_DEFERRED (1<<8) #define TX_LATE_COLL (1<<9) #define TX_COLL_CNT_MASK (0xF<<10) #define TX_PKT_RETRY (1<<31)#define MAC_TX_BUFF0_ADDR 0x4 #define TX_DMA_ENABLE (1<<0) #define TX_T_DONE (1<<1) #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)#define MAC_TX_BUFF0_LEN 0x8#define MAC_TX_BUFF1_STATUS 0x10#define MAC_TX_BUFF1_ADDR 0x14#define MAC_TX_BUFF1_LEN 0x18#define MAC_TX_BUFF2_STATUS 0x20#define MAC_TX_BUFF2_ADDR 0x24#define MAC_TX_BUFF2_LEN 0x28#define MAC_TX_BUFF3_STATUS 0x30#define MAC_TX_BUFF3_ADDR 0x34#define MAC_TX_BUFF3_LEN 0x38#define MAC0_RX_DMA_ADDR 0x14004100#define MAC1_RX_DMA_ADDR 0x14004300/* offsets from MAC_RX_RING_ADDR */#define MAC_RX_BUFF0_STATUS 0x0 #define RX_FRAME_LEN_MASK 0x3fff #define RX_WDOG_TIMER (1<<14) #define RX_RUNT (1<<15) #define RX_OVERLEN (1<<16) #define RX_COLL (1<<17) #define RX_ETHER (1<<18) #define RX_MII_ERROR (1<<19) #define RX_DRIBBLING (1<<20) #define RX_CRC_ERROR (1<<21) #define RX_VLAN1 (1<<22) #define RX_VLAN2 (1<<23) #define RX_LEN_ERROR (1<<24) #define RX_CNTRL_FRAME (1<<25) #define RX_U_CNTRL_FRAME (1<<26) #define RX_MCAST_FRAME (1<<27) #define RX_BCAST_FRAME (1<<28) #define RX_FILTER_FAIL (1<<29) #define RX_PACKET_FILTER (1<<30) #define RX_MISSED_FRAME (1<<31) #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)#define MAC_RX_BUFF0_ADDR 0x4 #define RX_DMA_ENABLE (1<<0) #define RX_T_DONE (1<<1) #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)#define MAC_RX_BUFF1_STATUS 0x10#define MAC_RX_BUFF1_ADDR 0x14#define MAC_RX_BUFF2_STATUS 0x20#define MAC_RX_BUFF2_ADDR 0x24#define MAC_RX_BUFF3_STATUS 0x30#define MAC_RX_BUFF3_ADDR 0x34/* UARTS 0-3 */#define UART0_ADDR 0x11100000#define UART1_ADDR 0x11200000#define UART2_ADDR 0x11300000#define UART3_ADDR 0x11400000#define UART_RX 0 /* Receive buffer */#define UART_TX 4 /* Transmit buffer */#define UART_IER 8 /* Interrupt Enable Register */#define UART_IIR 0xC /* Interrupt ID Register */#define UART_FCR 0x10 /* FIFO Control Register */#define UART_LCR 0x14 /* Line Control Register */#define UART_MCR 0x18 /* Modem Control Register */#define UART_LSR 0x1C /* Line Status Register */#define UART_MSR 0x20 /* Modem Status Register */#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */#define UART_MOD_CNTRL 0x100 /* Module Control */#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 *//* * These are the definitions for the Line Control Register */#define UART_LCR_SBC 0x40 /* Set break control */#define UART_LCR_SPAR 0x20 /* Stick parity (?) */#define UART_LCR_EPAR 0x10 /* Even parity select */#define UART_LCR_PARITY 0x08 /* Parity Enable */#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits *//* * These are the definitions for the Line Status Register */#define UART_LSR_TEMT 0x40 /* Transmitter empty */#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */#define UART_LSR_BI 0x10 /* Break interrupt indicator */#define UART_LSR_FE 0x08 /* Frame error indicator */#define UART_LSR_PE 0x04 /* Parity error indicator */#define UART_LSR_OE 0x02 /* Overrun error indicator */#define UART_LSR_DR 0x01 /* Receiver data ready *//* * These are the definitions for the Interrupt Identification Register */#define UART_IIR_NO_INT 0x01 /* No interrupts pending */#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */#define UART_IIR_MSI 0x00 /* Modem status interrupt */#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */#define UART_IIR_RDI 0x04 /* Receiver data interrupt */#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt *//* * These are the definitions for the Interrupt Enable Register */#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */#define UART_IER_RDI 0x01 /* Enable receiver data interrupt *//* * These are the definitions for the Modem Control Register */#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */#define UART_MCR_OUT2 0x08 /* Out2 complement */#define UART_MCR_OUT1 0x04 /* Out1 complement */#define UART_MCR_RTS 0x02 /* RTS complement */#define UART_MCR_DTR 0x01 /* DTR complement *//* * These are the definitions for the Modem Status Register */#define UART_MSR_DCD 0x80 /* Data Carrier Detect */#define UART_MSR_RI 0x40 /* Ring Indicator */#define UART_MSR_DSR 0x20 /* Data Set Ready */#define UART_MSR_CTS 0x10 /* Clear to Send */#define UART_MSR_DDCD 0x08 /* Delta DCD */#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */#define UART_MSR_DDSR 0x02 /* Delta DSR */#define UART_MSR_DCTS 0x01 /* Delta CTS */#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! *//* SSIO */#define SSI0_STATUS 0x11600000#define SSI0_INT 0x11600004#define SSI0_INT_ENABLE 0x11600008#define SSI0_CONFIG 0x11600020#define SSI0_ADATA 0x11600024#define SSI0_CLKDIV 0x11600028#define SSI0_CONTROL 0x11600100/* SSI1 */#define SSI1_STATUS 0x11680000#define SSI1_INT 0x11680004#define SSI1_INT_ENABLE 0x11680008#define SSI1_CONFIG 0x11680020#define SSI1_ADATA 0x11680024#define SSI1_CLKDIV 0x11680028#define SSI1_CONTROL 0x11680100/* IrDA Controller */#define IR_RING_PTR_STATUS 0x11500000#define IR_RING_BASE_ADDR_H 0x11500004#define IR_RING_BASE_ADDR_L 0x11500008#define IR_RING_SIZE 0x1150000C#define IR_RING_PROMPT 0x11500010#define IR_RING_ADDR_CMPR 0x11500014#define IR_CONFIG_1 0x11500020#define IR_SIR_FLAGS 0x11500024#define IR_ENABLE 0x11500028#define IR_READ_PHY_CONFIG 0x1150002C#define IR_WRITE_PHY_CONFIG 0x11500030#define IR_MAX_PKT_LEN 0x11500034#define IR_RX_BYTE_CNT 0x11500038#define IR_CONFIG_2 0x1150003C#define IR_INTERFACE_CONFIG 0x11500040/* GPIO */#define TSTATE_STATE_READ 0x11900100#define TSTATE_STATE_SET 0x11900100#define OUTPUT_STATE_READ 0x11900108#define OUTPUT_STATE_SET 0x11900108#define OUTPUT_STATE_CLEAR 0x1190010C#define PIN_STATE 0x11900110/* Power Management */#define PM_SCRATCH_0 0x11900018#define PM_SCRATCH_1 0x1190001C#define PM_WAKEUP_SOURCE_MASK 0x11900034#define PM_ENDIANESS 0x11900038#define PM_POWERUP_CONTROL 0x1190003C#define PM_WAKEUP_CAUSE 0x1190005C#define PM_SLEEP_POWER 0x11900078#define PM_SLEEP 0x1190007C/* Clock Controller */#define FQ_CNTRL_1 0x11900020#define FQ_CNTRL_2 0x11900024#define CLOCK_SOURCE_CNTRL 0x11900028#define CPU_PLL_CNTRL 0x11900060#define AUX_PLL_CNTRL 0x11900064/* AC97 Controller */#define AC97_CONFIG 0x10000000#define AC97_STATUS 0x10000004#define AC97_DATA 0x10000008#define AC97_CMD 0x1000000C#define AC97_CNTRL 0x10000010#endif⌨️ 快捷键说明
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