au1000.h

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/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Alchemy Semiconductor's Au1000 CPU.
 *
 * Copyright 2000 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	[e-mail] or [e-mail]
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _AU1000_H_
#define _AU1000_H_

/* SDRAM Controller */
#define CS_MODE_0                0x14000000
#define CS_MODE_1                0x14000004
#define CS_MODE_2                0x14000008

#define CS_CONFIG_0              0x1400000C
#define CS_CONFIG_1              0x14000010
#define CS_CONFIG_2              0x14000014

#define REFRESH_CONFIG           0x14000018
#define PRECHARGE_CMD            0x1400001C
#define AUTO_REFRESH_CMD         0x14000020

#define WRITE_EXTERN_0           0x14000024
#define WRITE_EXTERN_1           0x14000028
#define WRITE_EXTERN_2           0x1400002C

#define SDRAM_SLEEP              0x14000030
#define TOGGLE_CKE               0x14000034

/* Static Bus Controller */
#define STATIC_CONFIG_0          0x14001000
#define STATIC_TIMING_0          0x14001004
#define STATIC_ADDRESS_0         0x14001008

#define STATIC_CONFIG_1          0x14001010
#define STATIC_TIMING_1          0x14001014
#define STATIC_ADDRESS_1         0x14001018

#define STATIC_CONFIG_2          0x14001020
#define STATIC_TIMING_2          0x14001024
#define STATIC_ADDRESS_2         0x14001028

#define STATIC_CONFIG_3          0x14001030
#define STATIC_TIMING_3          0x14001034
#define STATIC_ADDRESS_3         0x14001038

/* DMA Controller 0 */
#define DMA0_MODE_SET            0x14002000
#define DMA0_MODE_CLEAR          0x14002004
#define DMA0_PERIPHERAL_ADDR     0x14002008
#define DMA0_BUFFER0_START       0x1400200C
#define DMA0_BUFFER0_COUNT       0x14002010
#define DMA0_BUFFER1_START       0x14002014
#define DMA0_BUFFER1_COUNT       0x14002018

/* DMA Controller 1 */
#define DMA1_MODE_SET            0x14002100
#define DMA1_MODE_CLEAR          0x14002104
#define DMA1_PERIPHERAL_ADDR     0x14002108
#define DMA1_BUFFER0_START       0x1400210C
#define DMA1_BUFFER0_COUNT       0x14002110
#define DMA1_BUFFER1_START       0x14002114
#define DMA1_BUFFER1_COUNT       0x14002118

/* DMA Controller 2 */
#define DMA2_MODE_SET            0x14002200
#define DMA2_MODE_CLEAR          0x14002204
#define DMA2_PERIPHERAL_ADDR     0x14002208
#define DMA2_BUFFER0_START       0x1400220C
#define DMA2_BUFFER0_COUNT       0x14002210
#define DMA2_BUFFER1_START       0x14002214
#define DMA2_BUFFER1_COUNT       0x14002218

/* DMA Controller 3 */
#define DMA3_MODE_SET            0x14002300
#define DMA3_MODE_CLEAR          0x14002304
#define DMA3_PERIPHERAL_ADDR     0x14002308
#define DMA3_BUFFER0_START       0x1400230C
#define DMA3_BUFFER0_COUNT       0x14002310
#define DMA3_BUFFER1_START       0x14002314
#define DMA3_BUFFER1_COUNT       0x14002318

/* DMA Controller 4 */
#define DMA4_MODE_SET            0x14002400
#define DMA4_MODE_CLEAR          0x14002404
#define DMA4_PERIPHERAL_ADDR     0x14002408
#define DMA4_BUFFER0_START       0x1400240C
#define DMA4_BUFFER0_COUNT       0x14002410
#define DMA4_BUFFER1_START       0x14002414
#define DMA4_BUFFER1_COUNT       0x14002418

/* DMA Controller 5 */
#define DMA5_MODE_SET            0x14002500
#define DMA5_MODE_CLEAR          0x14002504
#define DMA5_PERIPHERAL_ADDR     0x14002508
#define DMA5_BUFFER0_START       0x1400250C
#define DMA5_BUFFER0_COUNT       0x14002510
#define DMA5_BUFFER1_START       0x14002514
#define DMA5_BUFFER1_COUNT       0x14002518

/* DMA Controller 6 */
#define DMA6_MODE_SET            0x14002600
#define DMA6_MODE_CLEAR          0x14002604
#define DMA6_PERIPHERAL_ADDR     0x14002608
#define DMA6_BUFFER0_START       0x1400260C
#define DMA6_BUFFER0_COUNT       0x14002610
#define DMA6_BUFFER1_START       0x14002614
#define DMA6_BUFFER1_COUNT       0x14002618

/* DMA Controller 7 */
#define DMA7_MODE_SET            0x14002700
#define DMA7_MODE_CLEAR          0x14002704
#define DMA7_PERIPHERAL_ADDR     0x14002708
#define DMA7_BUFFER0_START       0x1400270C
#define DMA7_BUFFER0_COUNT       0x14002710
#define DMA7_BUFFER1_START       0x14002714
#define DMA7_BUFFER1_COUNT       0x14002718

/* Interrupt Controller 0 */
#define INTC0_CONFIG0_READ        0x10400040
#define INTC0_CONFIG0_SET         0x10400040
#define INTC0_CONFIG0_CLEAR       0x10400044

#define INTC0_CONFIG1_READ        0x10400048
#define INTC0_CONFIG1_SET         0x10400048
#define INTC0_CONFIG1_CLEAR       0x1040004C

#define INTC0_CONFIG2_READ        0x10400050
#define INTC0_CONFIG2_SET         0x10400050
#define INTC0_CONFIG2_CLEAR       0x10400054

#define INTC0_REQ0_INT            0x10400054
#define INTC0_SOURCE_READ         0x10400058
#define INTC0_SOURCE_SET          0x10400058
#define INTC0_SOURCE_CLEAR        0x1040005C
#define INTC0_REQ1_INT            0x1040005C

#define INTC0_ASSIGN_REQ_READ     0x10400060
#define INTC0_ASSIGN_REQ_SET      0x10400060
#define INTC0_ASSIGN_REQ_CLEAR    0x10400064

#define INTC0_WAKEUP_READ         0x10400068
#define INTC0_WAKEUP_SET          0x10400068
#define INTC0_WAKEUP_CLEAR        0x1040006C

#define INTC0_MASK_READ           0x10400070
#define INTC0_MASK_SET            0x10400070
#define INTC0_MASK_CLEAR          0x10400074

#define INTC0_R_EDGE_DETECT       0x10400078
#define INTC0_R_EDGE_DETECT_CLEAR 0x10400078
#define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C

#define INTC0_TEST_BIT            0x10400080

/* Interrupt Controller 1 */
#define INTC1_CONFIG0_READ        0x11800040
#define INTC1_CONFIG0_SET         0x11800040
#define INTC1_CONFIG0_CLEAR       0x11800044

#define INTC1_CONFIG1_READ        0x11800048
#define INTC1_CONFIG1_SET         0x11800048
#define INTC1_CONFIG1_CLEAR       0x1180004C

#define INTC1_CONFIG2_READ        0x11800050
#define INTC1_CONFIG2_SET         0x11800050
#define INTC1_CONFIG2_CLEAR       0x11800054

#define INTC1_REQ0_INT            0x11800054
#define INTC1_SOURCE_READ         0x11800058
#define INTC1_SOURCE_SET          0x11800058
#define INTC1_SOURCE_CLEAR        0x1180005C
#define INTC1_REQ1_INT            0x1180005C

#define INTC1_ASSIGN_REQ_READ     0x11800060
#define INTC1_ASSIGN_REQ_SET      0x11800060
#define INTC1_ASSIGN_REQ_CLEAR    0x11800064

#define INTC1_WAKEUP_READ         0x11800068
#define INTC1_WAKEUP_SET          0x11800068
#define INTC1_WAKEUP_CLEAR        0x1180006C

#define INTC1_MASK_READ           0x11800070
#define INTC1_MASK_SET            0x11800070
#define INTC1_MASK_CLEAR          0x11800074

#define INTC1_R_EDGE_DETECT       0x11800078
#define INTC1_R_EDGE_DETECT_CLEAR 0x11800078
#define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C

#define INTC1_TEST_BIT            0x11800080

/* Interrupt Configuration Modes */
#define INTC_INT_DISABLED                0
#define INTC_INT_RISE_EDGE             0x1
#define INTC_INT_FALL_EDGE             0x2
#define INTC_INT_RISE_AND_FALL_EDGE    0x3
#define INTC_INT_HIGH_LEVEL            0x5
#define INTC_INT_LOW_LEVEL             0x6
#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7

/* Interrupt Numbers */
#define AU1000_UART0_INT          0
#define AU1000_UART1_INT          1
#define AU1000_UART2_INT          2
#define AU1000_UART3_INT          3
#define AU1000_SSI0_INT           4
#define AU1000_SSI1_INT           5
#define AU1000_DMA0_INT           6
#define AU1000_DMA1_INT           7
#define AU1000_DMA2_INT           8
#define AU1000_DMA3_INT           9
#define AU1000_DMA4_INT           10
#define AU1000_DMA5_INT           11
#define AU1000_DMA6_INT           12
#define AU1000_DMA7_INT           13
#define AU1000_PC0_INT            14
#define AU1000_PC0_MATCH0_INT     15
#define AU1000_PC0_MATCH1_INT     16
#define AU1000_PC0_MATCH2_INT     17
#define AU1000_PC1_INT            18
#define AU1000_PC1_MATCH0_INT     19
#define AU1000_PC1_MATCH1_INT     20
#define AU1000_PC1_MATCH2_INT     21
#define AU1000_IRDA_TX_INT        22
#define AU1000_IRDA_RX_INT        23
#define AU1000_USB_DEV_REQ_INT    24
#define AU1000_USB_DEV_SUS_INT    25
#define AU1000_USB_HOST_INT       26
#define AU1000_ACSYNC_INT         27
#define AU1000_MAC0_DMA_INT       28
#define AU1000_MAC1_DMA_INT       29
#define AU1000_ETH0_IRQ           AU1000_MAC0_DMA_INT
#define AU1000_ETH1_IRQ           AU1000_MAC1_DMA_INT
#define AU1000_I2S_UO_INT         30
#define AU1000_AC97_INT           31
#define AU1000_LAST_INTC0_INT     AU1000_AC97_INT
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1000_GPIO_16            48
#define AU1000_GPIO_17            49
#define AU1000_GPIO_18            50
#define AU1000_GPIO_19            51
#define AU1000_GPIO_20            52
#define AU1000_GPIO_21            53
#define AU1000_GPIO_22            54
#define AU1000_GPIO_23            55
#define AU1000_GPIO_24            56
#define AU1000_GPIO_25            57
#define AU1000_GPIO_26            58
#define AU1000_GPIO_27            59
#define AU1000_GPIO_28            60
#define AU1000_GPIO_29            61
#define AU1000_GPIO_30            62
#define AU1000_GPIO_31            63

/* Programmable Counters 0 and 1 */
#define PC_BASE                   0x11900000
#define PC_COUNTER_CNTRL          (PC_BASE + 0x14)
  #define PC_CNTRL_E1S            (1<<23)
  #define PC_CNTRL_T1S            (1<<20)
  #define PC_CNTRL_M21            (1<<19)
  #define PC_CNTRL_M11            (1<<18)
  #define PC_CNTRL_M01            (1<<17)
  #define PC_CNTRL_C1S            (1<<16)
  #define PC_CNTRL_BP             (1<<14)
  #define PC_CNTRL_EN1            (1<<13)
  #define PC_CNTRL_BT1            (1<<12)
  #define PC_CNTRL_EN0            (1<<11)
  #define PC_CNTRL_BT0            (1<<10)
  #define PC_CNTRL_E0             (1<<8)
  #define PC_CNTRL_E0S            (1<<7)
  #define PC_CNTRL_32S            (1<<5)
  #define PC_CNTRL_T0S            (1<<4)
  #define PC_CNTRL_M20            (1<<3)
  #define PC_CNTRL_M10            (1<<2)
  #define PC_CNTRL_M00            (1<<1)
  #define PC_CNTRL_C0S            (1<<0)

/* Programmable Counter 0 Registers */