testadapter.v

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

`timescale 1ns/100ps
module testadapter;
    reg Clock50MHZ;
    reg Clock20MHZ;
    reg SampleCLKfromDM;
    reg BitStream;
    
    
    wire RST;
    wire SampleClock;
    wire [31:0]DataSRC;
    wire barkerflag,endflag,SPICONRST;
    wire SS,SCK,MOSI;
    
    parameter delay01=20,delay02=1000,delay03=50;
    parameter barkerflagt=14'b11_1111_0111_0011;
    parameter tailflag=32'b01010101_01010101_01010100_01111011;
    parameter tail=32'b00000000_00000000_01010101_01010101;
    integer i;
    BitStream2SPIAdapter adapter(Clock50MHZ,Clock20MHZ,RST,
       SampleCLKfromDM,BitStream,SampleClock,DataSRC,
       barkerflag,endflag,SPICONRST,
       SS,SCK,MOSI
       );
       
    always #(delay01/2) Clock50MHZ=~Clock50MHZ;
    always #(delay03/2) Clock20MHZ=~Clock20MHZ;
    always #(delay02/2) SampleCLKfromDM=~SampleCLKfromDM;
    
    initial
         begin 
                Clock50MHZ=0;
                Clock20MHZ=0;
                SampleCLKfromDM=0;
                BitStream=0;
         end
    initial
            begin
                for(i=10;i>=0;i=i-1)
                    #delay02 BitStream=0;
                for(i=13;i>=0;i=i-1)
                    #delay02 BitStream=barkerflagt[i];
                for(i=64;i>0;i=i-1)
                    #delay02 BitStream={$random}%2;
                for(i=31;i>=0;i=i-1)
                  #delay02 BitStream=tail[i];
                for(i=31;i>=0;i=i-1)
                   #delay02 BitStream=tailflag[i];
            end
    endmodule