bitstream2spiadapter.v.bak

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

`timescale 1ns / 100ps

module BitStream2SPIAdapter (Clock50MHzDCM,Clock20MHzDCM,RST,
                             SampleCLKfromDM,BitStream,SampleClock,DataSRC,
                             barkerflag,endflag,SPICONRST,
                             SS,SCK,MOSI
                                   );
   input Clock20MHzDCM;
	input  Clock50MHzDCM;		// Clock50MHz < system in >
	output RST;				// system reset < system out >
	 
	
	input  BitStream;		// bit stream data < system in >
	input  SampleCLKfromDM;		// sample clock < system in >
	

	output SCK;				// SPI sample clock < system out >
	output SS;				// SPI slave selection < system out >
	output MOSI;			// SPI data from Master to Slave < system out >
	output SampleClock;
	output SPICONRST;
	output [31:0]DataSRC;
	
	
	wire [31:0] DataSRC;
	output barkerflag;
	output endflag;
	
	wire RST;
	wire RSTCMP;
	wire BitStream;
	wire SampleCLKfromDM;
	wire SCK;
	wire SS;
	wire MOSI;
	wire SPICONRST;
	
	wire barkerflag;
	wire endflag;
	wire SampleClock;
	
	// DCM output clock signal
	wire Clock20MHzDCM;
	wire Clock50MHzDCM;
	
	// RSTG output signal
	wire SystemReset;
	
	// TSC output signal
	wire SPICONTRST;
	wire S_WforH_Flag;
	
	// SRC output signal
	wire [31:0] DatafromSRC;
	wire SampleCLK;
	
	// BCD output signal
	wire BarkerFlag;
	
	// EFD output signal
	wire EndFlag;
	
	// SPIC
	wire SPITX4096Flag;
	


	assign barkerflag		= BarkerFlag;
	assign endflag		= EndFlag;
	assign TestLED01		= S_WforH_Flag;
	assign SampleClock=SampleCLK;
	assign SPICONRST=SPICONTRST;

		
	assign RST				= SystemReset;
	assign DataSRC=DatafromSRC;
//	clock20mhz_dcm clock20mhz_dcm_instance
//	(
//		.CLKIN_IN(Clock50MHz), 
//		.RST_IN(), 
//		.CLKDV_OUT(Clock20MHzDCM), 
//		.CLKIN_IBUFG_OUT(), 
//		.CLK0_OUT(Clock50MHzDCM), 
//		.LOCKED_OUT()
//    );
	
	RSTGenerator RSTGenerator_instance
	(
		.Clock50MHz(Clock50MHzDCM), 		// Clock50MHzDCM < DCM >
		.RSTCMP(RSTCMP), 					// system reset compare signal < system out >
		.RST(SystemReset)					// system reset < out >
	);
	
	TotalSystemController TotalSystemController_instance
	(
		.Clock50MHz(Clock50MHzDCM),			// Clock50MHzDCM < DCM > 
		.SampleCLK(SampleCLK), 				// sample clock < system in >
		.RST(SystemReset), 					// system reset < RSTG >
		.BarkerFlag(BarkerFlag), 			// Barker flag < BCD >
		.TailFlag(EndFlag), 				// Tail flag < EFD >
		.SPICONTRST(SPICONTRST),			// SPI reset < out > 
		.S_WforH_Flag(S_WforH_Flag)
    );

	ShiftRegController ShiftRegController_instance
	(
		.Clock50MHz(Clock50MHzDCM),
		.BitStreamIn(BitStream), 
		.SampleCLKfromDM(SampleCLKfromDM),
		.SampleCLK(SampleCLK),				// sample clock < system in > 
		.DataOut(DatafromSRC)				// 32-bit data from the shift reg < out >
	);
	
	BarkerCodeDecision BarkerCodeDecision_instance
	(
		.Clock50MHz(Clock50MHzDCM), 		// Clock50MHzDCM < DCM >
		.RST(SystemReset), 					// system reset < RSTG >
		.SampleCLK(SampleCLK), 				// sample clock < system in >
		.DatafromSRC(DatafromSRC[12:0]),	// lowest 13-bit data from the shift reg < SRC > 
		.BarkerFlag(BarkerFlag)				// Barker flag < out >
    );
	
	EndFlagDecision EndFlagDecision_instance
	(
		.Clock50MHz(Clock50MHzDCM),			// Clock50MHzDCM < DCM > 
		.RST(SystemReset), 					// system reset < RSTG >
		.SampleCLK(SampleCLK), 				// sample clock < system in >
		.DatafromSRC(DatafromSRC), 			// 32-bit data from the shift reg < SRC >
		.EndFlag(EndFlag)					// Tail flag < out >
    );
	
	SPIController SPIController_instance
	(
		.Clock20MHz(Clock20MHzDCM), 		// Clock20MHz < DCM > 
		.RST(SystemReset), 					// system reset < RSTG >
		.SPICONTRST(SPICONTRST),			// SPI reset < TSC >  
		.DatafromSRC(DatafromSRC[31:0]), 	// most 8-bit data from the shift reg < SRC >
		.SCK(SCK), 							// SPI sample clock < system out > 
		.SS(SS), 							// SPI slave selection < system out >
		.MOSI(MOSI),
		.SPITX4096Flag(SPITX4096Flag)
    );
	
	
endmodule