spicontroller.v.bak

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

// 编写时间: 2008.01.06
// 最后更新: 2008.01.13
// 编写人员: 梁浩
// 版本编号: V1.0
// 功能描述: 该模块实现了SPI控制器
`timescale 1ns/100ps
module SPIController (Clock20MHz,RST,SPICONTRST,DatafromSRC,SCK,SS,MOSI,SPITX4096Flag);

	input  Clock20MHz;
	input  RST;
	
	input  SPICONTRST;
	input  [31:0] DatafromSRC;
	
	output SCK;
	output SS;
	output MOSI;
	
	output SPITX4096Flag;
	

   
	parameter S_LoadDatafromSRC	= 21'b0_0000_0000_0000_0000_0001;
	parameter S_SetDataFlag		= 21'b0_0000_0000_0000_0000_0010;
	parameter S_DataFlagDecision= 21'b0_0000_0000_0000_0000_0100;
	parameter S_SPI00			= 21'b0_0000_0000_0000_0000_1000;
	parameter S_SPI01			= 21'b0_0000_0000_0000_0001_0000;
	parameter S_SPI02			= 21'b0_0000_0000_0000_0010_0000;
	parameter S_SPI03			= 21'b0_0000_0000_0000_0100_0000;
	parameter S_SPI04			= 21'b0_0000_0000_0000_1000_0000;
	parameter S_SPI05			= 21'b0_0000_0000_0001_0000_0000;
	parameter S_SPI06			= 21'b0_0000_0000_0010_0000_0000;
	parameter S_SPI07			= 21'b0_0000_0000_0100_0000_0000;
	parameter S_SPI08			= 21'b0_0000_0000_1000_0000_0000;
	parameter S_SPI09			= 21'b0_0000_0001_0000_0000_0000;
	parameter S_SPI10			= 21'b0_0000_0010_0000_0000_0000;
	parameter S_SPI11			= 21'b0_0000_0100_0000_0000_0000;
	parameter S_SPI12			= 21'b0_0000_1000_0000_0000_0000;
	parameter S_SPI13			= 21'b0_0001_0000_0000_0000_0000;
	parameter S_SPI14			= 21'b0_0010_0000_0000_0000_0000;
	parameter S_SPI15			= 21'b0_0100_0000_0000_0000_0000;
	parameter S_ModDataFlag		= 21'b0_1000_0000_0000_0000_0000;
	parameter S_IDLE			= 21'b1_0000_0000_0000_0000_0000;

	reg [31:0] DatafromSRCReg;
	reg [3:0]  DataFlag 	= 4'b0000;
	reg [20:0] StateofSPI;
	reg SCK;
	reg SS;
	reg [7:0] SPIDataReg   = 8'b0000_0000;
	reg [2:0] CONT4MHz     = 3'b000;
	reg SPITX4096Flag;
	reg [12:0] SPITXCONT = 13'b0_0000_0000_0000;
	
	assign MOSI	= SPIDataReg[7];
	
	always@(posedge Clock20MHz)
	begin
		if(RST == 1'b0)
		begin
			CONT4MHz	<= 3'b000;
		end
		else if(CONT4MHz == 3'b100)
		begin
			CONT4MHz	<= 3'b000;
		end
		else
		begin
			CONT4MHz	<= CONT4MHz + 1'b1;
		end
	end
	
	always@(posedge Clock20MHz)
	begin
		if(RST == 1'b0)
		begin
			StateofSPI	<= S_IDLE;
		end
		else
		begin
			case(StateofSPI)
				S_LoadDatafromSRC:
				begin
					StateofSPI	<= S_SetDataFlag;
				end
				S_SetDataFlag:
				begin
					StateofSPI	<= S_DataFlagDecision;
				end
				S_DataFlagDecision:
				begin
					if((CONT4MHz == 3'b100) && (DataFlag == 4'b0000))
					begin
						StateofSPI	<= S_IDLE;
					end
					else if((CONT4MHz == 3'b100) && (DataFlag != 4'b0000))
					begin
						StateofSPI	<= S_SPI00;
					end
				end
				S_SPI00: // SPI Initialization
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI01;
					end
				end
				S_SPI01: // the 1st posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI02;
					end
				end
				S_SPI02: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI03;
					end
				end
				S_SPI03: // the 2nd posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI04;
					end
				end
				S_SPI04: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI05;
					end
				end
				S_SPI05: // the 3rd posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI06;
					end
				end
				S_SPI06: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI07;
					end
				end
				S_SPI07: // the 4th posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI08;
					end
				end
				S_SPI08: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI09;
					end
				end
				S_SPI09: // the 5th posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI10;
					end
				end
				S_SPI10: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI11;
					end
				end
				S_SPI11: // the 6th posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI12;
					end
				end
				S_SPI12: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI13;
					end
				end
				S_SPI13: // the 7th posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI14;
					end
				end
				S_SPI14: // change the data on MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI15;
					end
				end
				S_SPI15: // the 8th posedge of SCK to sample MOSI
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_ModDataFlag;
					end
				end
				S_ModDataFlag:
				begin
					if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_IDLE;
					end
				end
				S_IDLE: // SPI idle 
				begin
					if(SPICONTRST == 1'b0)
					begin
						StateofSPI	<= S_LoadDatafromSRC;
					end
					else if(DataFlag == 4'b0000)
					begin
						StateofSPI	<= S_IDLE;
					end
					else if(CONT4MHz == 3'b100)
					begin
						StateofSPI	<= S_SPI00;
					end
				end
			endcase
		end
	end
	
	always@(posedge Clock20MHz)
	begin
		case(StateofSPI)
			S_LoadDatafromSRC:
			begin
				DatafromSRCReg	<= DatafromSRC;
			end
			S_SetDataFlag:
			begin
				DataFlag		<= 4'b1111;
			end
			S_SPI00: // SPI Initialization
			begin
				if((CONT4MHz == 3'b100) && (DataFlag == 4'b1111))
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= DatafromSRCReg[31:24];
				end
				else if((CONT4MHz == 3'b100) && (DataFlag == 4'b0111))
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= DatafromSRCReg[23:16];
				end
				else if((CONT4MHz == 3'b100) && (DataFlag == 4'b0011))
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= DatafromSRCReg[15:8];
				end
				else if((CONT4MHz == 3'b100) && (DataFlag == 4'b0001))
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= DatafromSRCReg[7:0];
				end
			end
			S_SPI01: // the 1st posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI02: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI03: // the 2nd posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI04: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI05: // the 3rd posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI06: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI07: // the 4th posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI08: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI09: // the 5th posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI10: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI11: // the 6th posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI12: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI13: // the 7th posedge of SCK to sample MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin			
					SCK			<= 1'b1;
					SS			<= 1'b0;
				end
			end
			S_SPI14: // change the data on MOSI
			begin
				if(CONT4MHz == 3'b100)
				begin
					SCK			<= 1'b0;
					SS			<= 1'b0;
					SPIDataReg	<= {SPIDataReg[6:0],1'b0};
				end
			end
			S_SPI15: // the 8th posedge of SCK to sample MOSI
			begin
				if((CONT4MHz == 3'b100) && (SPITXCONT == 13'b1_0000_0000_0000))
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
					SPITXCONT	<= 13'b0_0000_0000_0001;
				end
				else if((CONT4MHz == 3'b100) && (SPITXCONT != 13'b1_0000_0000_0000))
				begin
					SCK			<= 1'b1;
					SS			<= 1'b0;
					SPITXCONT	<= SPITXCONT + 1'b1;
				end
			end
			S_ModDataFlag:
			begin
				if(CONT4MHz == 3'b100)
				begin
					DataFlag		<= {1'b0,DataFlag[3:1]};
					SCK				<= 1'b0;
					SS				<= 1'b1;
				end
			end
			S_IDLE: // SPI idle
			begin
				if(SPITXCONT == 13'b1_0000_0000_0000)
				begin
					SPITX4096Flag	<= 1'b1;
				end
				else if(SPITXCONT != 13'b1_0000_0000_0000)
				begin
					SPITX4096Flag	<= 1'b0;
				end					
			end
		endcase
	end


endmodule