endflagdecision.v.bak

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

// 编写时间: 2008.01.05
// 最后更新: 2008.01.05
// 编写人员: 梁浩
// 版本编号: V1.0
// 功能描述: 该模块实现了传输数据结束标志的判断
`timescale 1ns/100ps
module EndFlagDecision (Clock50MHz,RST,SampleCLK,DatafromSRC,EndFlag);

	input  Clock50MHz;
	input  RST;
	input  SampleCLK;
	input  [31:0] DatafromSRC;
	
	output EndFlag;
	
	
	parameter S_WaitforCMPResValid	= 3'b001; 	// wait for the TailDecision2nd to be valid
	parameter S_DotheComparation 	= 3'b010; 	// do the comparation with the TailFlag
	parameter S_IDLE				= 3'b100; 	// idle
	
	parameter TAILFLAG			= 32'b0000_0000_0000_0000_0000_0001_1011_1001;

	reg SampleVofSCLKLT	= 1'b0; // Last Time sample value of the Sample Clock 
	reg SampleVofSCLKCT	= 1'b0; // Current Time sample value of the Sample Clock	
	reg EndFlag			= 1'b0;
	reg [2:0] StateofEFD;
	
	wire [31:0] TailDecision1st;
	wire TailDecision2nd;
	
	assign TailDecision1st[0]	= DatafromSRC[0] ^~ 1'b1;
	assign TailDecision1st[1]	= DatafromSRC[1] ^~ 1'b0;
	assign TailDecision1st[2]	= DatafromSRC[2] ^~ 1'b0;
	assign TailDecision1st[3]	= DatafromSRC[3] ^~ 1'b1;
	assign TailDecision1st[4]	= DatafromSRC[4] ^~ 1'b1;
	assign TailDecision1st[5]	= DatafromSRC[5] ^~ 1'b1;
	assign TailDecision1st[6]	= DatafromSRC[6] ^~ 1'b0;
	assign TailDecision1st[7]	= DatafromSRC[7] ^~ 1'b1;
	assign TailDecision1st[8]	= DatafromSRC[8] ^~ 1'b1;
	assign TailDecision1st[9]	= DatafromSRC[9] ^~ 1'b0;
	assign TailDecision1st[10]	= DatafromSRC[10] ^~ 1'b0;
	assign TailDecision1st[11]	= DatafromSRC[11] ^~ 1'b0;
	assign TailDecision1st[12]	= DatafromSRC[12] ^~ 1'b0;
	assign TailDecision1st[13]	= DatafromSRC[13] ^~ 1'b0;
	assign TailDecision1st[14]	= DatafromSRC[14] ^~ 1'b0;
	assign TailDecision1st[15]	= DatafromSRC[15] ^~ 1'b0;
	assign TailDecision1st[16]	= DatafromSRC[16] ^~ 1'b0;
	assign TailDecision1st[17]	= DatafromSRC[17] ^~ 1'b0;
	assign TailDecision1st[18]	= DatafromSRC[18] ^~ 1'b0;
	assign TailDecision1st[19]	= DatafromSRC[19] ^~ 1'b0;
	assign TailDecision1st[20]	= DatafromSRC[20] ^~ 1'b0;
	assign TailDecision1st[21]	= DatafromSRC[21] ^~ 1'b0;
	assign TailDecision1st[22]	= DatafromSRC[22] ^~ 1'b0;
	assign TailDecision1st[23]	= DatafromSRC[23] ^~ 1'b0;
	assign TailDecision1st[24]	= DatafromSRC[24] ^~ 1'b0;
	assign TailDecision1st[25]	= DatafromSRC[25] ^~ 1'b0;
	assign TailDecision1st[26]	= DatafromSRC[26] ^~ 1'b0;
	assign TailDecision1st[27]	= DatafromSRC[27] ^~ 1'b0;
	assign TailDecision1st[28]	= DatafromSRC[28] ^~ 1'b0;
	assign TailDecision1st[29]	= DatafromSRC[29] ^~ 1'b0;
	assign TailDecision1st[30]	= DatafromSRC[30] ^~ 1'b0;
	assign TailDecision1st[31]	= DatafromSRC[31] ^~ 1'b0;	
	
	assign TailDecision2nd		= TailDecision1st[0] && TailDecision1st[1] && TailDecision1st[2] &&
								  TailDecision1st[3] && TailDecision1st[4] && TailDecision1st[5] &&
								  TailDecision1st[6] && TailDecision1st[7] && TailDecision1st[8] &&
								  TailDecision1st[9] && TailDecision1st[10] && TailDecision1st[11] &&
								  TailDecision1st[12] && TailDecision1st[13] && TailDecision1st[14] &&
								  TailDecision1st[15] && TailDecision1st[16] && TailDecision1st[17] &&
								  TailDecision1st[18] && TailDecision1st[19] && TailDecision1st[20] &&
								  TailDecision1st[21] && TailDecision1st[22] && TailDecision1st[23] &&
								  TailDecision1st[24] && TailDecision1st[25] && TailDecision1st[26] &&
								  TailDecision1st[27] && TailDecision1st[28] && TailDecision1st[29] &&
								  TailDecision1st[30] && TailDecision1st[31];

	always@(posedge Clock50MHz)
	begin
		SampleVofSCLKCT	<= SampleCLK;
		SampleVofSCLKLT	<= SampleVofSCLKCT;
	end
	
	always@(posedge Clock50MHz)
	begin
		case(StateofEFD)
			S_WaitforCMPResValid:
			begin
				if(RST == 1'b0)
				begin
					StateofEFD	<= S_IDLE;
				end
				else
				begin
					StateofEFD	<= S_DotheComparation;
				end
			end
			S_DotheComparation:
			begin
				StateofEFD		<= S_IDLE;
			end
			S_IDLE:
			begin
				if({SampleVofSCLKLT,SampleVofSCLKCT} == 2'b01)
				begin
					StateofEFD	<= S_WaitforCMPResValid;
				end
				else
				begin
					StateofEFD	<= S_IDLE;
				end
			end
			default:
			begin
				StateofEFD		<= S_IDLE;
			end
		endcase
	end
	
	always@(posedge Clock50MHz)
	begin
		case(StateofEFD)
			S_DotheComparation:
			begin
				if(TailDecision2nd == 1'b1)
				begin
					EndFlag	<= 1'b1;
				end
				else
				begin
					EndFlag	<= 1'b0;
				end
			end
		endcase
	end
	

endmodule