_primary.vhd

来自「用Verilog 实现将比特流数据转化为SPI协议数据的适配器」· VHDL 代码 · 共 38 行

library verilog;
use verilog.vl_types.all;
entity SPIController is
    generic(
        S_LoadDatafromSRC: integer := 1;
        S_SetDataFlag   : integer := 2;
        S_DataFlagDecision: integer := 4;
        S_SPI00         : integer := 8;
        S_SPI01         : integer := 16;
        S_SPI02         : integer := 32;
        S_SPI03         : integer := 64;
        S_SPI04         : integer := 128;
        S_SPI05         : integer := 256;
        S_SPI06         : integer := 512;
        S_SPI07         : integer := 1024;
        S_SPI08         : integer := 2048;
        S_SPI09         : integer := 4096;
        S_SPI10         : integer := 8192;
        S_SPI11         : integer := 16384;
        S_SPI12         : integer := 32768;
        S_SPI13         : integer := 65536;
        S_SPI14         : integer := 131072;
        S_SPI15         : integer := 262144;
        S_ModDataFlag   : integer := 524288;
        S_IDLE          : integer := 1048576
    );
    port(
        Clock20MHz      : in     vl_logic;
        RST             : in     vl_logic;
        SPICONTRST      : in     vl_logic;
        DatafromSRC     : in     vl_logic_vector(31 downto 0);
        SCK             : out    vl_logic;
        SS              : out    vl_logic;
        MOSI            : out    vl_logic;
        SPITX4096Flag   : out    vl_logic
    );
end SPIController;