_primary.vhd

来自「用Verilog 实现将比特流数据转化为SPI协议数据的适配器」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity BitStream2SPIAdapter is
    port(
        Clock50MHzDCM   : in     vl_logic;
        Clock20MHzDCM   : in     vl_logic;
        RST             : out    vl_logic;
        SampleCLKfromDM : in     vl_logic;
        BitStream       : in     vl_logic;
        SampleClock     : out    vl_logic;
        DataSRC         : out    vl_logic_vector(31 downto 0);
        barkerflag      : out    vl_logic;
        endflag         : out    vl_logic;
        SPICONRST       : out    vl_logic;
        SS              : out    vl_logic;
        SCK             : out    vl_logic;
        MOSI            : out    vl_logic
    );
end BitStream2SPIAdapter;