_primary.vhd

用Verilog 实现将比特流数据转化为SPI协议数据的适配器

library verilog;
use verilog.vl_types.all;
entity RSTGenerator is
    port(
        Clock50MHz      : in     vl_logic;
        RSTCMP          : out    vl_logic;
        RST             : out    vl_logic
    );
end RSTGenerator;