yiziqi.v

来自「这是一个等精度测频得硬件描述语言编写的程序」· Verilog 代码 · 共 20 行

module yiziqi(pk,clk,shuchu,shineng);
input pk;
input clk;
output  [7:0] shuchu;
output shineng;
reg [7:0] shuchu;
reg shineng;
reg [16:0]ppkk;
reg [8:0] p;
reg [7:0] k;
     reg clk;
reg n,m;
always @ (posedge clk)
if(clk)
begin
ppkk[16]<=pk;
ppkk=(ppkk>>1);
end
endmodule