📄 jichunqi.rpt
字号:
71 - - A -- OUTPUT 0 0 0 0 shuju1
30 - - - 18 OUTPUT 0 0 0 0 shuju2
94 - - - 19 OUTPUT 0 0 0 0 shuju3
84 - - - 05 OUTPUT 0 0 0 0 shuju4
57 - - C -- OUTPUT 0 0 0 0 shuju5
87 - - - 12 OUTPUT 0 0 0 0 shuju6
10 - - A -- OUTPUT 0 0 0 0 shuju7
97 - - - 23 OUTPUT 0 0 0 0 shuju8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\jichunqi\jichunqi.rpt
jichunqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 10 DFFE + 1 0 1 0 :181
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\jichunqi\jichunqi.rpt
jichunqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\jichunqi\jichunqi.rpt
jichunqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 1 load
Device-Specific Information: f:\jichunqi\jichunqi.rpt
jichunqi
** EQUATIONS **
load : INPUT;
-- Node name is 'dizi0'
-- Equation name is 'dizi0', type is output
dizi0 = GND;
-- Node name is 'dizi1'
-- Equation name is 'dizi1', type is output
dizi1 = GND;
-- Node name is 'dizi2'
-- Equation name is 'dizi2', type is output
dizi2 = GND;
-- Node name is 'dizi3'
-- Equation name is 'dizi3', type is output
dizi3 = GND;
-- Node name is 'dizi4'
-- Equation name is 'dizi4', type is output
dizi4 = GND;
-- Node name is 'dizi5'
-- Equation name is 'dizi5', type is output
dizi5 = GND;
-- Node name is 'dizi6'
-- Equation name is 'dizi6', type is output
dizi6 = GND;
-- Node name is 'dizi7'
-- Equation name is 'dizi7', type is output
dizi7 = GND;
-- Node name is 'dizi8'
-- Equation name is 'dizi8', type is output
dizi8 = GND;
-- Node name is 'nload'
-- Equation name is 'nload', type is output
nload = _LC6_C10;
-- Node name is 'shuju0'
-- Equation name is 'shuju0', type is output
shuju0 = GND;
-- Node name is 'shuju1'
-- Equation name is 'shuju1', type is output
shuju1 = GND;
-- Node name is 'shuju2'
-- Equation name is 'shuju2', type is output
shuju2 = GND;
-- Node name is 'shuju3'
-- Equation name is 'shuju3', type is output
shuju3 = GND;
-- Node name is 'shuju4'
-- Equation name is 'shuju4', type is output
shuju4 = GND;
-- Node name is 'shuju5'
-- Equation name is 'shuju5', type is output
shuju5 = GND;
-- Node name is 'shuju6'
-- Equation name is 'shuju6', type is output
shuju6 = GND;
-- Node name is 'shuju7'
-- Equation name is 'shuju7', type is output
shuju7 = GND;
-- Node name is 'shuju8'
-- Equation name is 'shuju8', type is output
shuju8 = GND;
-- Node name is ':181'
-- Equation name is '_LC6_C10', type is buried
_LC6_C10 = DFFE(!load, GLOBAL(!load), VCC, VCC, VCC);
Project Information f:\jichunqi\jichunqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,391K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -