jichunqi.v

来自「这个程序可以用作寄存器的使用」· Verilog 代码 · 共 23 行

module jichunqi(clk,load,shuru,shuju,dizi,nload);
input shuru;
output [8:0]shuju,dizi;
input clk,load;
reg [8:0]shuju,dizi;
reg n;
output nload;
reg nload;
reg [19:0]data;
always@(posedge clk or posedge load )
if (load )
begin
data[0]<=shuru;
data<=(data<<1);
end
always@( negedge load )
begin
{shuju,dizi}=data;
nload=~load;
end
endmodule