📄 toptop.rpt
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_LC2_A9 = LCELL( _EQ025);
_EQ025 = _LC1_A9 & _LC4_A9;
-- Node name is '|dizishengcheng:3|lpm_add_sub:54|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ026);
_EQ026 = _LC2_A9 & _LC3_A6 & _LC6_A6;
-- Node name is '|dizishengcheng:3|lpm_add_sub:54|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ027);
_EQ027 = _LC2_A9 & _LC3_A6 & _LC6_A6 & _LC8_A6;
-- Node name is '|dizishengcheng:3|lpm_add_sub:54|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ028);
_EQ028 = _LC1_A6 & _LC2_A6;
-- Node name is '|dizishengcheng:3|lpm_add_sub:54|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ029);
_EQ029 = _LC1_A6 & _LC2_A6 & _LC4_A6 & _LC4_A18;
-- Node name is '|dizishengcheng:3|lpm_add_sub:54|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = LCELL( _EQ030);
_EQ030 = _LC5_A18 & _LC6_A18;
-- Node name is '|dizishengcheng:3|:16'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ031, clk0, VCC, VCC, wren);
_EQ031 = _LC1_A18 & !_LC7_A18
# _LC1_A18 & !_LC3_A18
# !_LC1_A18 & _LC3_A18 & _LC7_A18;
-- Node name is '|dizishengcheng:3|:17'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = DFFE( _EQ032, clk0, VCC, VCC, wren);
_EQ032 = _LC3_A18 & !_LC6_A18
# _LC3_A18 & !_LC5_A18
# !_LC3_A18 & _LC5_A18 & _LC6_A18;
-- Node name is '|dizishengcheng:3|:18'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = DFFE( _EQ033, clk0, VCC, VCC, wren);
_EQ033 = !_LC5_A18 & _LC6_A18
# _LC5_A18 & !_LC6_A18;
-- Node name is '|dizishengcheng:3|:19'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE( _EQ034, clk0, VCC, VCC, wren);
_EQ034 = _LC4_A6 & !_LC7_A6
# _LC4_A6 & !_LC4_A18
# !_LC4_A6 & _LC4_A18 & _LC7_A6;
-- Node name is '|dizishengcheng:3|:20'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = DFFE( _EQ035, clk0, VCC, VCC, wren);
_EQ035 = !_LC1_A6 & _LC4_A18
# !_LC2_A6 & _LC4_A18
# _LC1_A6 & _LC2_A6 & !_LC4_A18;
-- Node name is '|dizishengcheng:3|:21'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = DFFE( _EQ036, clk0, VCC, VCC, wren);
_EQ036 = _LC1_A6 & !_LC2_A6
# !_LC1_A6 & _LC2_A6;
-- Node name is '|dizishengcheng:3|:22'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = DFFE( _EQ037, clk0, VCC, VCC, wren);
_EQ037 = !_LC5_A6 & _LC8_A6
# _LC5_A6 & !_LC8_A6;
-- Node name is '|dizishengcheng:3|:23'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = DFFE( _EQ038, clk0, VCC, VCC, wren);
_EQ038 = !_LC3_A6 & _LC6_A6
# !_LC2_A9 & _LC6_A6
# _LC2_A9 & _LC3_A6 & !_LC6_A6;
-- Node name is '|dizishengcheng:3|:24'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = DFFE( _EQ039, clk0, VCC, VCC, wren);
_EQ039 = !_LC2_A9 & _LC3_A6
# _LC2_A9 & !_LC3_A6;
-- Node name is '|dizishengcheng:3|:25'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ040, clk0, VCC, VCC, wren);
_EQ040 = !_LC1_A9 & _LC4_A9
# _LC1_A9 & !_LC4_A9;
-- Node name is '|dizishengcheng:3|:26'
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = DFFE(!_LC4_A9, clk0, VCC, VCC, wren);
-- Node name is '|dizishengcheng:3|:38'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ041);
_EQ041 = _LC1_A18 & _LC3_A18 & _LC5_A18 & _LC6_A18;
-- Node name is '|dizishengcheng:3|:52'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( VCC, clk0, VCC, VCC, _LC8_A18);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_0' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC9_C', type is memory
_EC9_C = MEMORY_SEGMENT( datain0, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_1' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC9_A', type is memory
_EC9_A = MEMORY_SEGMENT( datain1, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_2' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC1_A', type is memory
_EC1_A = MEMORY_SEGMENT( datain2, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_3' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC9_B', type is memory
_EC9_B = MEMORY_SEGMENT( datain3, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_4' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC1_B', type is memory
_EC1_B = MEMORY_SEGMENT( datain4, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_5' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC9_E', type is memory
_EC9_E = MEMORY_SEGMENT( datain5, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_6' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC1_E', type is memory
_EC1_E = MEMORY_SEGMENT( datain6, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
-- Node name is '|ram:5|altdpram:altdpram_component|segment0_7' from file "altdpram.tdf" line 163, column 13
-- Equation name is '_EC1_C', type is memory
_EC1_C = MEMORY_SEGMENT( datain7, VCC, VCC, wren, rden, _LC4_A9, _LC1_A9, _LC3_A6, _LC6_A6, _LC8_A6, _LC1_A6, _LC4_A18, _LC4_A6, _LC6_A18, _LC3_A18, _LC1_A18, _LC1_E12, _LC4_E7, _LC1_E7, _LC3_E7, _LC6_E7, _LC8_E7, _LC3_E12, _LC6_E12, _LC8_E12, _LC2_E12, _LC4_E12, VCC, VCC, VCC);
Project Information f:\zuixin\toptop.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,540K
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