📄 toptop.rpt
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Device-Specific Information: f:\zuixin\toptop.rpt
toptop
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A6 8/ 8(100%) 5/ 8( 62%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
A9 3/ 8( 37%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
A18 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
B27 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 11/22( 50%)
B32 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
E7 8/ 8(100%) 5/ 8( 62%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
E12 8/ 8(100%) 6/ 8( 75%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A37 2/16( 12%) 2/16( 12%) 0/16( 0%) 0/2 3/6 26/88( 29%)
B37 2/16( 12%) 0/16( 0%) 2/16( 12%) 0/2 3/6 26/88( 29%)
C37 2/16( 12%) 2/16( 12%) 0/16( 0%) 0/2 3/6 26/88( 29%)
E37 2/16( 12%) 2/16( 12%) 0/16( 0%) 0/2 3/6 26/88( 29%)
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 16/141 ( 11%)
Total logic cells used: 45/1728 ( 2%)
Total embedded cells used: 8/96 ( 8%)
Total EABs used: 4/6 ( 66%)
Average fan-in: 3.11/4 ( 77%)
Total fan-in: 140/6912 ( 2%)
Total input pins required: 14
Total input I/O cell registers required: 0
Total output pins required: 2
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 45
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 1/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 8 0 0 3 0 0 0 0 0 0 0 0 8 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19/2
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 8 0 0 0 0 2 0 0 0 0 10/2
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/2
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 8 0 0 0 0 8 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/2
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 8 8 0 3 0 0 8 0 0 0 0 0 8 8 0 0 0 0 0 0 0 0 8 0 0 0 0 2 0 0 0 0 45/8
Device-Specific Information: f:\zuixin\toptop.rpt
toptop
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
14 - - B -- INPUT ^ 0 0 0 20 clk
199 - - - 29 INPUT ^ 0 0 0 12 clk0
15 - - B -- INPUT ^ 0 0 0 9 clk1
208 - - - 36 INPUT ^ 0 0 0 1 datain0
207 - - - 35 INPUT ^ 0 0 0 1 datain1
206 - - - 34 INPUT ^ 0 0 0 1 datain2
205 - - - 34 INPUT ^ 0 0 0 1 datain3
204 - - - 33 INPUT ^ 0 0 0 1 datain4
203 - - - 32 INPUT ^ 0 0 0 1 datain5
202 - - - 31 INPUT ^ 0 0 0 1 datain6
200 - - - 30 INPUT ^ 0 0 0 1 datain7
13 - - B -- INPUT ^ 0 0 0 19 rden
12 - - B -- INPUT ^ 0 0 0 9 rest
11 - - A -- INPUT ^ 0 0 0 19 wren
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zuixin\toptop.rpt
toptop
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- OUTPUT 0 1 0 0 dout
8 - - A -- OUTPUT 0 1 0 0 zhongduan
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zuixin\toptop.rpt
toptop
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 27 DFFE 3 2 0 1 |bingxingru:4|data7 (|bingxingru:4|:38)
- 8 - B 27 DFFE 3 2 0 1 |bingxingru:4|data6 (|bingxingru:4|:39)
- 7 - B 27 DFFE 3 2 0 1 |bingxingru:4|data5 (|bingxingru:4|:40)
- 6 - B 27 DFFE 3 2 0 1 |bingxingru:4|data4 (|bingxingru:4|:41)
- 5 - B 27 DFFE 3 2 0 1 |bingxingru:4|data3 (|bingxingru:4|:42)
- 4 - B 27 DFFE 3 2 0 1 |bingxingru:4|data2 (|bingxingru:4|:43)
- 3 - B 27 DFFE 3 2 0 1 |bingxingru:4|data1 (|bingxingru:4|:44)
- 2 - B 27 DFFE 3 1 0 1 |bingxingru:4|data0 (|bingxingru:4|:45)
- 4 - B 32 DFFE 2 2 1 0 |bingxingru:4|:50
- 5 - E 07 AND2 0 3 0 4 |diziduqu:6|lpm_add_sub:37|addcore:adder|:87
- 7 - E 07 AND2 0 2 0 1 |diziduqu:6|lpm_add_sub:37|addcore:adder|:91
- 2 - E 07 AND2 0 4 0 4 |diziduqu:6|lpm_add_sub:37|addcore:adder|:99
- 7 - E 12 AND2 0 2 0 1 |diziduqu:6|lpm_add_sub:37|addcore:adder|:103
- 5 - E 12 AND2 0 4 0 2 |diziduqu:6|lpm_add_sub:37|addcore:adder|:111
- 4 - E 12 DFFE 2 2 0 8 |diziduqu:6|:15
- 2 - E 12 DFFE 2 1 0 9 |diziduqu:6|:16
- 8 - E 12 DFFE 2 2 0 9 |diziduqu:6|:17
- 6 - E 12 DFFE 2 2 0 10 |diziduqu:6|:18
- 3 - E 12 DFFE 2 1 0 11 |diziduqu:6|:19
- 8 - E 07 DFFE 2 2 0 9 |diziduqu:6|:20
- 6 - E 07 DFFE 2 2 0 10 |diziduqu:6|:21
- 3 - E 07 DFFE 2 1 0 11 |diziduqu:6|:22
- 1 - E 07 DFFE 2 2 0 9 |diziduqu:6|:23
- 4 - E 07 DFFE 2 1 0 10 |diziduqu:6|:24
- 1 - E 12 DFFE 2 0 0 11 |diziduqu:6|:25
- 2 - A 09 AND2 0 2 0 4 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:83
- 5 - A 06 AND2 0 3 0 1 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:91
- 2 - A 06 AND2 0 4 0 4 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:95
- 7 - A 06 AND2 0 2 0 1 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:99
- 5 - A 18 AND2 0 4 0 4 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:107
- 7 - A 18 AND2 0 2 0 1 |dizishengcheng:3|lpm_add_sub:54|addcore:adder|:111
- 1 - A 18 DFFE 2 2 0 9 |dizishengcheng:3|:16
- 3 - A 18 DFFE 2 2 0 10 |dizishengcheng:3|:17
- 6 - A 18 DFFE 2 1 0 11 |dizishengcheng:3|:18
- 4 - A 06 DFFE 2 2 0 9 |dizishengcheng:3|:19
- 4 - A 18 DFFE 2 2 0 10 |dizishengcheng:3|:20
- 1 - A 06 DFFE 2 1 0 11 |dizishengcheng:3|:21
- 8 - A 06 DFFE 2 1 0 9 |dizishengcheng:3|:22
- 6 - A 06 DFFE 2 2 0 10 |dizishengcheng:3|:23
- 3 - A 06 DFFE 2 1 0 11 |dizishengcheng:3|:24
- 1 - A 09 DFFE 2 1 0 9 |dizishengcheng:3|:25
- 4 - A 09 DFFE 2 0 0 10 |dizishengcheng:3|:26
- 8 - A 18 AND2 0 4 0 1 |dizishengcheng:3|:38
- 2 - A 18 DFFE 1 1 1 0 |dizishengcheng:3|:52
- - 9 C -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_0
- - 9 A -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_1
- - 1 A -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_2
- - 9 B -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_3
- - 1 B -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_4
- - 9 E -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_5
- - 1 E -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_6
- - 1 C -- MEM_SGMT 3 22 0 1 |ram:5|altdpram:altdpram_component|segment0_7
- 1 - B 32 SOFT s ! 1 0 0 1 rest~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\zuixin\toptop.rpt
toptop
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 19/144( 13%) 11/ 72( 15%) 1/ 72( 1%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 17/144( 11%) 21/ 72( 29%) 0/ 72( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
C: 5/144( 3%) 21/ 72( 29%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 17/144( 11%) 11/ 72( 15%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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